// SPDX-License-Identifier: GPL-2.0+
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/*
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* BRIEF MODULE DESCRIPTION
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* PCI init for Ralink RT2880 solution
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*
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* Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
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*
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* May 2007 Bruce Chang
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* Initial Release
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*
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* May 2009 Bruce Chang
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* support RT2880/RT3883 PCIe
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*
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* May 2011 Bruce Chang
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* support RT6855/MT7620 PCIe
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/gpio/consumer.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/sys_soc.h>
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#include <mt7621.h>
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#include <ralink_regs.h>
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#include "../../pci/pci.h"
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/* sysctl */
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#define MT7621_GPIO_MODE 0x60
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/* MediaTek specific configuration registers */
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#define PCIE_FTS_NUM 0x70c
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#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
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#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
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/* rt_sysc_membase relative registers */
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#define RALINK_CLKCFG1 0x30
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/* Host-PCI bridge registers */
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#define RALINK_PCI_PCICFG_ADDR 0x0000
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#define RALINK_PCI_PCIMSK_ADDR 0x000C
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#define RALINK_PCI_CONFIG_ADDR 0x0020
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#define RALINK_PCI_CONFIG_DATA 0x0024
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#define RALINK_PCI_MEMBASE 0x0028
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#define RALINK_PCI_IOBASE 0x002C
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/* PCICFG virtual bridges */
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#define PCIE_P2P_CNT 3
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#define PCIE_P2P_BR_DEVNUM_SHIFT(p) (16 + (p) * 4)
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#define PCIE_P2P_BR_DEVNUM0_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(0)
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#define PCIE_P2P_BR_DEVNUM1_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(1)
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#define PCIE_P2P_BR_DEVNUM2_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(2)
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#define PCIE_P2P_BR_DEVNUM_MASK 0xf
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#define PCIE_P2P_BR_DEVNUM_MASK_FULL (0xfff << PCIE_P2P_BR_DEVNUM0_SHIFT)
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/* PCIe RC control registers */
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#define MT7621_PCIE_OFFSET 0x2000
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#define MT7621_NEXT_PORT 0x1000
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#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
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#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
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#define RALINK_PCI_ID 0x0030
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#define RALINK_PCI_CLASS 0x0034
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#define RALINK_PCI_SUBID 0x0038
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#define RALINK_PCI_STATUS 0x0050
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/* Some definition values */
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#define PCIE_REVISION_ID BIT(0)
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#define PCIE_CLASS_CODE (0x60400 << 8)
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#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
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#define PCIE_BAR_ENABLE BIT(0)
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#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
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#define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
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#define PCIE_PORT_LINKUP BIT(0)
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#define MEMORY_BASE 0x0
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#define PERST_MODE_MASK GENMASK(11, 10)
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#define PERST_MODE_GPIO BIT(10)
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#define PERST_DELAY_MS 100
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/**
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* struct mt7621_pcie_port - PCIe port information
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* @base: I/O mapped register base
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* @list: port list
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* @pcie: pointer to PCIe host info
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* @phy: pointer to PHY control block
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* @pcie_rst: pointer to port reset control
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* @gpio_rst: gpio reset
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* @slot: port slot
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* @irq: GIC irq
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* @enabled: indicates if port is enabled
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*/
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struct mt7621_pcie_port {
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void __iomem *base;
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struct list_head list;
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struct mt7621_pcie *pcie;
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struct phy *phy;
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struct reset_control *pcie_rst;
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struct gpio_desc *gpio_rst;
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u32 slot;
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int irq;
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bool enabled;
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};
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/**
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* struct mt7621_pcie - PCIe host information
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* @base: IO Mapped Register Base
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* @io: IO resource
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* @mem: non-prefetchable memory resource
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* @busn: bus range
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* @offset: IO / Memory offset
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* @dev: Pointer to PCIe device
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* @io_map_base: virtual memory base address for io
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* @ports: pointer to PCIe port information
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* @irq_map: irq mapping info according pcie link status
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* @resets_inverted: depends on chip revision
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* reset lines are inverted.
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*/
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struct mt7621_pcie {
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void __iomem *base;
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struct device *dev;
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struct resource io;
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struct resource mem;
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struct resource busn;
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struct {
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resource_size_t mem;
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resource_size_t io;
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} offset;
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unsigned long io_map_base;
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struct list_head ports;
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int irq_map[PCIE_P2P_CNT];
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bool resets_inverted;
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};
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static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
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{
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return readl(pcie->base + reg);
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}
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static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
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{
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writel(val, pcie->base + reg);
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}
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static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
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{
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u32 val = readl(pcie->base + reg);
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val &= ~clr;
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val |= set;
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writel(val, pcie->base + reg);
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}
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static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
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{
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return readl(port->base + reg);
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}
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static inline void pcie_port_write(struct mt7621_pcie_port *port,
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u32 val, u32 reg)
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{
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writel(val, port->base + reg);
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}
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static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
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(func << 8) | (where & 0xfc) | 0x80000000;
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}
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static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct mt7621_pcie *pcie = bus->sysdata;
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u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
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return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
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}
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struct pci_ops mt7621_pci_ops = {
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.map_bus = mt7621_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
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{
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
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}
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static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
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u32 reg, u32 val)
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{
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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}
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static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
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{
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if (port->gpio_rst)
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gpiod_set_value(port->gpio_rst, 1);
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}
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static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
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{
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if (port->gpio_rst)
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gpiod_set_value(port->gpio_rst, 0);
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}
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static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
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{
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return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
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}
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static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port)
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{
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rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1);
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}
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static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
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{
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rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
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}
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static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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if (pcie->resets_inverted)
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reset_control_assert(port->pcie_rst);
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else
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reset_control_deassert(port->pcie_rst);
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}
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static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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if (pcie->resets_inverted)
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reset_control_deassert(port->pcie_rst);
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else
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reset_control_assert(port->pcie_rst);
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}
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static void setup_cm_memory_region(struct mt7621_pcie *pcie)
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{
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struct resource *mem_resource = &pcie->mem;
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struct device *dev = pcie->dev;
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resource_size_t mask;
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if (mips_cps_numiocu(0)) {
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/*
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* FIXME: hardware doesn't accept mask values with 1s after
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* 0s (e.g. 0xffef), so it would be great to warn if that's
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* about to happen
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*/
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mask = ~(mem_resource->end - mem_resource->start);
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write_gcr_reg1_base(mem_resource->start);
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write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
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(unsigned long long)read_gcr_reg1_base(),
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(unsigned long long)read_gcr_reg1_mask());
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}
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}
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static int mt7621_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
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{
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struct mt7621_pcie *pcie = pdev->bus->sysdata;
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struct device *dev = pcie->dev;
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int irq = pcie->irq_map[slot];
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dev_info(dev, "bus=%d slot=%d irq=%d\n", pdev->bus->number, slot, irq);
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return irq;
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}
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static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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int err;
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if (of_pci_range_parser_init(&parser, node)) {
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dev_err(dev, "missing \"ranges\" property\n");
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return -EINVAL;
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}
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for_each_of_pci_range(&parser, &range) {
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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pcie->io_map_base =
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(unsigned long)ioremap(range.cpu_addr,
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range.size);
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of_pci_range_to_resource(&range, node, &pcie->io);
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pcie->io.start = range.cpu_addr;
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pcie->io.end = range.cpu_addr + range.size - 1;
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pcie->offset.io = 0x00000000UL;
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break;
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case IORESOURCE_MEM:
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of_pci_range_to_resource(&range, node, &pcie->mem);
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pcie->offset.mem = 0x00000000UL;
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break;
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}
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}
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err = of_pci_parse_bus_range(node, &pcie->busn);
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if (err < 0) {
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dev_err(dev, "failed to parse bus ranges property: %d\n", err);
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pcie->busn.name = node->name;
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pcie->busn.start = 0;
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pcie->busn.end = 0xff;
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pcie->busn.flags = IORESOURCE_BUS;
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}
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set_io_port_base(pcie->io_map_base);
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return 0;
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}
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static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
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struct device_node *node,
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int slot)
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{
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struct mt7621_pcie_port *port;
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struct device *dev = pcie->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct device_node *pnode = dev->of_node;
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struct resource regs;
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char name[10];
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int err;
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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err = of_address_to_resource(pnode, slot + 1, ®s);
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if (err) {
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dev_err(dev, "missing \"reg\" property\n");
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return err;
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}
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port->base = devm_ioremap_resource(dev, ®s);
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if (IS_ERR(port->base))
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return PTR_ERR(port->base);
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snprintf(name, sizeof(name), "pcie%d", slot);
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port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
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if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
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dev_err(dev, "failed to get pcie%d reset control\n", slot);
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return PTR_ERR(port->pcie_rst);
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}
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snprintf(name, sizeof(name), "pcie-phy%d", slot);
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port->phy = devm_phy_get(dev, name);
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if (IS_ERR(port->phy) && slot != 1)
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return PTR_ERR(port->phy);
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port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
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GPIOD_OUT_LOW);
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if (IS_ERR(port->gpio_rst)) {
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dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
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return PTR_ERR(port->gpio_rst);
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}
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port->slot = slot;
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port->pcie = pcie;
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port->irq = platform_get_irq(pdev, slot);
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if (port->irq < 0) {
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dev_err(dev, "Failed to get IRQ for PCIe%d\n", slot);
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return -ENXIO;
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}
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INIT_LIST_HEAD(&port->list);
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list_add_tail(&port->list, &pcie->ports);
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return 0;
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}
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static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node, *child;
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struct resource regs;
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int err;
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err = of_address_to_resource(node, 0, ®s);
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if (err) {
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dev_err(dev, "missing \"reg\" property\n");
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return err;
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}
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pcie->base = devm_ioremap_resource(dev, ®s);
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if (IS_ERR(pcie->base))
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return PTR_ERR(pcie->base);
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for_each_available_child_of_node(node, child) {
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int slot;
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err = of_pci_get_devfn(child);
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if (err < 0) {
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of_node_put(child);
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dev_err(dev, "failed to parse devfn: %d\n", err);
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return err;
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}
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slot = PCI_SLOT(err);
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err = mt7621_pcie_parse_port(pcie, child, slot);
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if (err) {
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of_node_put(child);
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return err;
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}
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}
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return 0;
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}
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static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
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{
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struct mt7621_pcie *pcie = port->pcie;
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struct device *dev = pcie->dev;
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u32 slot = port->slot;
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int err;
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err = phy_init(port->phy);
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if (err) {
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dev_err(dev, "failed to initialize port%d phy\n", slot);
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return err;
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}
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err = phy_power_on(port->phy);
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if (err) {
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dev_err(dev, "failed to power on port%d phy\n", slot);
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phy_exit(port->phy);
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return err;
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}
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port->enabled = true;
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return 0;
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}
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static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
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{
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struct mt7621_pcie_port *port;
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list_for_each_entry(port, &pcie->ports, list) {
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/* PCIe RC reset assert */
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mt7621_control_assert(port);
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/* PCIe EP reset assert */
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mt7621_rst_gpio_pcie_assert(port);
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}
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mdelay(PERST_DELAY_MS);
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}
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static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
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{
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struct mt7621_pcie_port *port;
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list_for_each_entry(port, &pcie->ports, list)
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mt7621_control_deassert(port);
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}
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static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
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{
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struct mt7621_pcie_port *port;
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list_for_each_entry(port, &pcie->ports, list)
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mt7621_rst_gpio_pcie_deassert(port);
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mdelay(PERST_DELAY_MS);
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}
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static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct mt7621_pcie_port *port, *tmp;
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int err;
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rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
|
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mt7621_pcie_reset_assert(pcie);
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mt7621_pcie_reset_rc_deassert(pcie);
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list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
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u32 slot = port->slot;
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if (slot == 1) {
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port->enabled = true;
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continue;
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}
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err = mt7621_pcie_init_port(port);
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if (err) {
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dev_err(dev, "Initiating port %d failed\n", slot);
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list_del(&port->list);
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}
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}
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mt7621_pcie_reset_ep_deassert(pcie);
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tmp = NULL;
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list_for_each_entry(port, &pcie->ports, list) {
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u32 slot = port->slot;
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if (!mt7621_pcie_port_is_linkup(port)) {
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dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
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slot);
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mt7621_control_assert(port);
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mt7621_pcie_port_clk_disable(port);
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port->enabled = false;
|
|
if (slot == 0) {
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tmp = port;
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continue;
|
}
|
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if (slot == 1 && tmp && !tmp->enabled)
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phy_power_off(tmp->phy);
|
|
}
|
}
|
}
|
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static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
|
{
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struct mt7621_pcie *pcie = port->pcie;
|
u32 slot = port->slot;
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u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
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u32 val;
|
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/* enable pcie interrupt */
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val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
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val |= PCIE_PORT_INT_EN(slot);
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pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
|
|
/* map 2G DDR region */
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pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
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offset + RALINK_PCI_BAR0SETUP_ADDR);
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pcie_write(pcie, MEMORY_BASE,
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offset + RALINK_PCI_IMBASEBAR0_ADDR);
|
|
/* configure class code and revision ID */
|
pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
|
offset + RALINK_PCI_CLASS);
|
}
|
|
static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
|
{
|
struct device *dev = pcie->dev;
|
struct mt7621_pcie_port *port;
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u8 num_slots_enabled = 0;
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u32 slot;
|
u32 val;
|
|
/* Setup MEMWIN and IOWIN */
|
pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
|
pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
|
|
list_for_each_entry(port, &pcie->ports, list) {
|
if (port->enabled) {
|
mt7621_pcie_port_clk_enable(port);
|
mt7621_pcie_enable_port(port);
|
dev_info(dev, "PCIE%d enabled\n", port->slot);
|
num_slots_enabled++;
|
}
|
}
|
|
for (slot = 0; slot < num_slots_enabled; slot++) {
|
val = read_config(pcie, slot, PCI_COMMAND);
|
val |= PCI_COMMAND_MASTER;
|
write_config(pcie, slot, PCI_COMMAND, val);
|
/* configure RC FTS number to 250 when it leaves L0s */
|
val = read_config(pcie, slot, PCIE_FTS_NUM);
|
val &= ~PCIE_FTS_NUM_MASK;
|
val |= PCIE_FTS_NUM_L0(0x50);
|
write_config(pcie, slot, PCIE_FTS_NUM, val);
|
}
|
}
|
|
static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
|
{
|
u32 pcie_link_status = 0;
|
u32 n = 0;
|
int i = 0;
|
u32 p2p_br_devnum[PCIE_P2P_CNT];
|
int irqs[PCIE_P2P_CNT];
|
struct mt7621_pcie_port *port;
|
|
list_for_each_entry(port, &pcie->ports, list) {
|
u32 slot = port->slot;
|
|
irqs[i++] = port->irq;
|
if (port->enabled)
|
pcie_link_status |= BIT(slot);
|
}
|
|
if (pcie_link_status == 0)
|
return -1;
|
|
/*
|
* Assign device numbers from zero to the enabled ports,
|
* then assigning remaining device numbers to any disabled
|
* ports.
|
*/
|
for (i = 0; i < PCIE_P2P_CNT; i++)
|
if (pcie_link_status & BIT(i))
|
p2p_br_devnum[i] = n++;
|
|
for (i = 0; i < PCIE_P2P_CNT; i++)
|
if ((pcie_link_status & BIT(i)) == 0)
|
p2p_br_devnum[i] = n++;
|
|
pcie_rmw(pcie, RALINK_PCI_PCICFG_ADDR,
|
PCIE_P2P_BR_DEVNUM_MASK_FULL,
|
(p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) |
|
(p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) |
|
(p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT));
|
|
/* Assign IRQs */
|
n = 0;
|
for (i = 0; i < PCIE_P2P_CNT; i++)
|
if (pcie_link_status & BIT(i))
|
pcie->irq_map[n++] = irqs[i];
|
|
for (i = n; i < PCIE_P2P_CNT; i++)
|
pcie->irq_map[i] = -1;
|
|
return 0;
|
}
|
|
static void mt7621_pcie_add_resources(struct mt7621_pcie *pcie,
|
struct list_head *res)
|
{
|
pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
|
pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
|
}
|
|
static int mt7621_pcie_register_host(struct pci_host_bridge *host,
|
struct list_head *res)
|
{
|
struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
|
|
list_splice_init(res, &host->windows);
|
host->busnr = pcie->busn.start;
|
host->dev.parent = pcie->dev;
|
host->ops = &mt7621_pci_ops;
|
host->map_irq = mt7621_map_irq;
|
host->swizzle_irq = pci_common_swizzle;
|
host->sysdata = pcie;
|
|
return pci_host_probe(host);
|
}
|
|
static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
|
{ .soc_id = "mt7621", .revision = "E2" }
|
};
|
|
static int mt7621_pci_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
const struct soc_device_attribute *attr;
|
struct mt7621_pcie *pcie;
|
struct pci_host_bridge *bridge;
|
int err;
|
LIST_HEAD(res);
|
|
if (!dev->of_node)
|
return -ENODEV;
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
|
if (!bridge)
|
return -ENOMEM;
|
|
pcie = pci_host_bridge_priv(bridge);
|
pcie->dev = dev;
|
platform_set_drvdata(pdev, pcie);
|
INIT_LIST_HEAD(&pcie->ports);
|
|
attr = soc_device_match(mt7621_pci_quirks_match);
|
if (attr)
|
pcie->resets_inverted = true;
|
|
err = mt7621_pcie_parse_dt(pcie);
|
if (err) {
|
dev_err(dev, "Parsing DT failed\n");
|
return err;
|
}
|
|
err = mt7621_pci_parse_request_of_pci_ranges(pcie);
|
if (err) {
|
dev_err(dev, "Error requesting pci resources from ranges");
|
return err;
|
}
|
|
/* set resources limits */
|
ioport_resource.start = pcie->io.start;
|
ioport_resource.end = pcie->io.end;
|
|
mt7621_pcie_init_ports(pcie);
|
|
err = mt7621_pcie_init_virtual_bridges(pcie);
|
if (err) {
|
dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
|
return 0;
|
}
|
|
mt7621_pcie_enable_ports(pcie);
|
|
setup_cm_memory_region(pcie);
|
|
mt7621_pcie_add_resources(pcie, &res);
|
|
err = mt7621_pcie_register_host(bridge, &res);
|
if (err) {
|
dev_err(dev, "Error registering host\n");
|
return err;
|
}
|
|
return 0;
|
}
|
|
static const struct of_device_id mt7621_pci_ids[] = {
|
{ .compatible = "mediatek,mt7621-pci" },
|
{},
|
};
|
MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
|
|
static struct platform_driver mt7621_pci_driver = {
|
.probe = mt7621_pci_probe,
|
.driver = {
|
.name = "mt7621-pci",
|
.of_match_table = of_match_ptr(mt7621_pci_ids),
|
},
|
};
|
|
builtin_platform_driver(mt7621_pci_driver);
|
