// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI OMAP4 ISS V4L2 Driver - CSI PHY module
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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*
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* Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/regmap.h>
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#include "../../../../arch/arm/mach-omap2/control.h"
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#include "iss.h"
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#include "iss_regs.h"
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#include "iss_csiphy.h"
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/*
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* csiphy_lanes_config - Configuration of CSIPHY lanes.
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*
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* Updates HW configuration.
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* Called with phy->mutex taken.
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*/
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static void csiphy_lanes_config(struct iss_csiphy *phy)
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{
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unsigned int i;
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u32 reg;
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reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG);
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for (i = 0; i < phy->max_data_lanes; i++) {
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reg &= ~(CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) |
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CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i + 1));
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reg |= (phy->lanes.data[i].pol ?
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CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) : 0);
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reg |= (phy->lanes.data[i].pos <<
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CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i + 1));
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}
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reg &= ~(CSI2_COMPLEXIO_CFG_CLOCK_POL |
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CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK);
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reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0;
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reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT;
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iss_reg_write(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG, reg);
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}
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/*
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* csiphy_set_power
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* @power: Power state to be set.
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*
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* Returns 0 if successful, or -EBUSY if the retry count is exceeded.
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*/
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static int csiphy_set_power(struct iss_csiphy *phy, u32 power)
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{
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u32 reg;
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u8 retry_count;
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iss_reg_update(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG,
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CSI2_COMPLEXIO_CFG_PWD_CMD_MASK,
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power | CSI2_COMPLEXIO_CFG_PWR_AUTO);
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retry_count = 0;
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do {
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udelay(1);
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reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG)
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& CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK;
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if (reg != power >> 2)
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retry_count++;
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} while ((reg != power >> 2) && (retry_count < 250));
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if (retry_count == 250) {
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dev_err(phy->iss->dev, "CSI2 CIO set power failed!\n");
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return -EBUSY;
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}
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return 0;
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}
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/*
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* csiphy_dphy_config - Configure CSI2 D-PHY parameters.
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*
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* Called with phy->mutex taken.
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*/
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static void csiphy_dphy_config(struct iss_csiphy *phy)
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{
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u32 reg;
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/* Set up REGISTER0 */
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reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT;
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reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT;
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iss_reg_write(phy->iss, phy->phy_regs, REGISTER0, reg);
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/* Set up REGISTER1 */
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reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT;
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reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT;
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reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT;
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reg |= 0xb8 << REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT;
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iss_reg_write(phy->iss, phy->phy_regs, REGISTER1, reg);
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}
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/*
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* TCLK values are OK at their reset values
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*/
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#define TCLK_TERM 0
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#define TCLK_MISS 1
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#define TCLK_SETTLE 14
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int omap4iss_csiphy_config(struct iss_device *iss,
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struct v4l2_subdev *csi2_subdev)
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{
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struct iss_csi2_device *csi2 = v4l2_get_subdevdata(csi2_subdev);
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struct iss_pipeline *pipe = to_iss_pipeline(&csi2_subdev->entity);
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struct iss_v4l2_subdevs_group *subdevs = pipe->external->host_priv;
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struct iss_csiphy_dphy_cfg csi2phy;
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int csi2_ddrclk_khz;
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struct iss_csiphy_lanes_cfg *lanes;
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unsigned int used_lanes = 0;
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u32 cam_rx_ctrl;
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unsigned int i;
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lanes = &subdevs->bus.csi2.lanecfg;
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/*
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* SCM.CONTROL_CAMERA_RX
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* - bit [31] : CSIPHY2 lane 2 enable (4460+ only)
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* - bit [30:29] : CSIPHY2 per-lane enable (1 to 0)
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* - bit [28:24] : CSIPHY1 per-lane enable (4 to 0)
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* - bit [21] : CSIPHY2 CTRLCLK enable
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* - bit [20:19] : CSIPHY2 config: 00 d-phy, 01/10 ccp2
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* - bit [18] : CSIPHY1 CTRLCLK enable
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* - bit [17:16] : CSIPHY1 config: 00 d-phy, 01/10 ccp2
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*/
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/*
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* TODO: When implementing DT support specify the CONTROL_CAMERA_RX
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* register offset in the syscon property instead of hardcoding it.
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*/
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regmap_read(iss->syscon, 0x68, &cam_rx_ctrl);
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if (subdevs->interface == ISS_INTERFACE_CSI2A_PHY1) {
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cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI21_LANEENABLE_MASK |
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OMAP4_CAMERARX_CSI21_CAMMODE_MASK);
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/* NOTE: Leave CSIPHY1 config to 0x0: D-PHY mode */
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/* Enable all lanes for now */
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cam_rx_ctrl |=
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0x1f << OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT;
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/* Enable CTRLCLK */
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cam_rx_ctrl |= OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK;
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}
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if (subdevs->interface == ISS_INTERFACE_CSI2B_PHY2) {
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cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI22_LANEENABLE_MASK |
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OMAP4_CAMERARX_CSI22_CAMMODE_MASK);
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/* NOTE: Leave CSIPHY2 config to 0x0: D-PHY mode */
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/* Enable all lanes for now */
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cam_rx_ctrl |=
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0x3 << OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT;
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/* Enable CTRLCLK */
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cam_rx_ctrl |= OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK;
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}
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regmap_write(iss->syscon, 0x68, cam_rx_ctrl);
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/* Reset used lane count */
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csi2->phy->used_data_lanes = 0;
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/* Clock and data lanes verification */
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for (i = 0; i < csi2->phy->max_data_lanes; i++) {
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if (lanes->data[i].pos == 0)
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continue;
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if (lanes->data[i].pol > 1 ||
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lanes->data[i].pos > (csi2->phy->max_data_lanes + 1))
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return -EINVAL;
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if (used_lanes & (1 << lanes->data[i].pos))
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return -EINVAL;
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used_lanes |= 1 << lanes->data[i].pos;
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csi2->phy->used_data_lanes++;
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}
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if (lanes->clk.pol > 1 ||
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lanes->clk.pos > (csi2->phy->max_data_lanes + 1))
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return -EINVAL;
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if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
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return -EINVAL;
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csi2_ddrclk_khz = pipe->external_rate / 1000
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/ (2 * csi2->phy->used_data_lanes)
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* pipe->external_bpp;
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/*
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* THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1.
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* THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3.
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*/
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csi2phy.ths_term = DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1;
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csi2phy.ths_settle = DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3;
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csi2phy.tclk_term = TCLK_TERM;
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csi2phy.tclk_miss = TCLK_MISS;
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csi2phy.tclk_settle = TCLK_SETTLE;
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mutex_lock(&csi2->phy->mutex);
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csi2->phy->dphy = csi2phy;
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csi2->phy->lanes = *lanes;
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mutex_unlock(&csi2->phy->mutex);
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return 0;
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}
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int omap4iss_csiphy_acquire(struct iss_csiphy *phy)
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{
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int rval;
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mutex_lock(&phy->mutex);
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rval = omap4iss_csi2_reset(phy->csi2);
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if (rval)
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goto done;
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csiphy_dphy_config(phy);
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csiphy_lanes_config(phy);
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rval = csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_ON);
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if (rval)
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goto done;
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phy->phy_in_use = 1;
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done:
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mutex_unlock(&phy->mutex);
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return rval;
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}
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void omap4iss_csiphy_release(struct iss_csiphy *phy)
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{
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mutex_lock(&phy->mutex);
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if (phy->phy_in_use) {
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csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_OFF);
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phy->phy_in_use = 0;
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}
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mutex_unlock(&phy->mutex);
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}
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/*
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* omap4iss_csiphy_init - Initialize the CSI PHY frontends
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*/
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int omap4iss_csiphy_init(struct iss_device *iss)
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{
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struct iss_csiphy *phy1 = &iss->csiphy1;
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struct iss_csiphy *phy2 = &iss->csiphy2;
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phy1->iss = iss;
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phy1->csi2 = &iss->csi2a;
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phy1->max_data_lanes = ISS_CSIPHY1_NUM_DATA_LANES;
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phy1->used_data_lanes = 0;
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phy1->cfg_regs = OMAP4_ISS_MEM_CSI2_A_REGS1;
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phy1->phy_regs = OMAP4_ISS_MEM_CAMERARX_CORE1;
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mutex_init(&phy1->mutex);
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phy2->iss = iss;
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phy2->csi2 = &iss->csi2b;
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phy2->max_data_lanes = ISS_CSIPHY2_NUM_DATA_LANES;
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phy2->used_data_lanes = 0;
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phy2->cfg_regs = OMAP4_ISS_MEM_CSI2_B_REGS1;
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phy2->phy_regs = OMAP4_ISS_MEM_CAMERARX_CORE2;
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mutex_init(&phy2->mutex);
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return 0;
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}
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