// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI OMAP4 ISS V4L2 Driver
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*
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* Copyright (C) 2012, Texas Instruments
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*
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* Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/vmalloc.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ctrls.h>
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#include "iss.h"
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#include "iss_regs.h"
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#define ISS_PRINT_REGISTER(iss, name)\
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dev_dbg(iss->dev, "###ISS " #name "=0x%08x\n", \
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iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_##name))
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static void iss_print_status(struct iss_device *iss)
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{
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dev_dbg(iss->dev, "-------------ISS HL Register dump-------------\n");
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ISS_PRINT_REGISTER(iss, HL_REVISION);
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ISS_PRINT_REGISTER(iss, HL_SYSCONFIG);
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ISS_PRINT_REGISTER(iss, HL_IRQSTATUS(5));
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ISS_PRINT_REGISTER(iss, HL_IRQENABLE_SET(5));
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ISS_PRINT_REGISTER(iss, HL_IRQENABLE_CLR(5));
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ISS_PRINT_REGISTER(iss, CTRL);
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ISS_PRINT_REGISTER(iss, CLKCTRL);
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ISS_PRINT_REGISTER(iss, CLKSTAT);
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dev_dbg(iss->dev, "-----------------------------------------------\n");
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}
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/*
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* omap4iss_flush - Post pending L3 bus writes by doing a register readback
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* @iss: OMAP4 ISS device
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*
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* In order to force posting of pending writes, we need to write and
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* readback the same register, in this case the revision register.
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*
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* See this link for reference:
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* https://www.mail-archive.com/linux-omap@vger.kernel.org/msg08149.html
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*/
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static void omap4iss_flush(struct iss_device *iss)
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{
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION, 0);
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iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION);
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}
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/*
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* iss_isp_enable_interrupts - Enable ISS ISP interrupts.
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* @iss: OMAP4 ISS device
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*/
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static void omap4iss_isp_enable_interrupts(struct iss_device *iss)
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{
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static const u32 isp_irq = ISP5_IRQ_OCP_ERR |
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ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR |
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ISP5_IRQ_RSZ_FIFO_OVF |
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ISP5_IRQ_RSZ_INT_DMA |
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ISP5_IRQ_ISIF_INT(0);
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/* Enable ISP interrupts */
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQSTATUS(0), isp_irq);
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQENABLE_SET(0),
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isp_irq);
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}
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/*
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* iss_isp_disable_interrupts - Disable ISS interrupts.
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* @iss: OMAP4 ISS device
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*/
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static void omap4iss_isp_disable_interrupts(struct iss_device *iss)
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{
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQENABLE_CLR(0), ~0);
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}
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/*
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* iss_enable_interrupts - Enable ISS interrupts.
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* @iss: OMAP4 ISS device
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*/
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static void iss_enable_interrupts(struct iss_device *iss)
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{
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static const u32 hl_irq = ISS_HL_IRQ_CSIA | ISS_HL_IRQ_CSIB
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| ISS_HL_IRQ_ISP(0);
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/* Enable HL interrupts */
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5), hl_irq);
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQENABLE_SET(5), hl_irq);
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if (iss->regs[OMAP4_ISS_MEM_ISP_SYS1])
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omap4iss_isp_enable_interrupts(iss);
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}
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/*
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* iss_disable_interrupts - Disable ISS interrupts.
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* @iss: OMAP4 ISS device
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*/
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static void iss_disable_interrupts(struct iss_device *iss)
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{
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if (iss->regs[OMAP4_ISS_MEM_ISP_SYS1])
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omap4iss_isp_disable_interrupts(iss);
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQENABLE_CLR(5), ~0);
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}
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int omap4iss_get_external_info(struct iss_pipeline *pipe,
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struct media_link *link)
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{
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struct iss_device *iss =
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container_of(pipe, struct iss_video, pipe)->iss;
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struct v4l2_subdev_format fmt;
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struct v4l2_ctrl *ctrl;
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int ret;
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if (!pipe->external)
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return 0;
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if (pipe->external_rate)
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return 0;
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memset(&fmt, 0, sizeof(fmt));
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fmt.pad = link->source->index;
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fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
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ret = v4l2_subdev_call(media_entity_to_v4l2_subdev(link->sink->entity),
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pad, get_fmt, NULL, &fmt);
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if (ret < 0)
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return -EPIPE;
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pipe->external_bpp = omap4iss_video_format_info(fmt.format.code)->bpp;
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ctrl = v4l2_ctrl_find(pipe->external->ctrl_handler,
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V4L2_CID_PIXEL_RATE);
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if (!ctrl) {
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dev_warn(iss->dev, "no pixel rate control in subdev %s\n",
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pipe->external->name);
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return -EPIPE;
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}
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pipe->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
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return 0;
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}
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/*
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* Configure the bridge. Valid inputs are
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*
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* IPIPEIF_INPUT_CSI2A: CSI2a receiver
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* IPIPEIF_INPUT_CSI2B: CSI2b receiver
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*
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* The bridge and lane shifter are configured according to the selected input
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* and the ISP platform data.
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*/
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void omap4iss_configure_bridge(struct iss_device *iss,
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enum ipipeif_input_entity input)
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{
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u32 issctrl_val;
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u32 isp5ctrl_val;
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issctrl_val = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_CTRL);
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issctrl_val &= ~ISS_CTRL_INPUT_SEL_MASK;
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issctrl_val &= ~ISS_CTRL_CLK_DIV_MASK;
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isp5ctrl_val = iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL);
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switch (input) {
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case IPIPEIF_INPUT_CSI2A:
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issctrl_val |= ISS_CTRL_INPUT_SEL_CSI2A;
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break;
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case IPIPEIF_INPUT_CSI2B:
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issctrl_val |= ISS_CTRL_INPUT_SEL_CSI2B;
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break;
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default:
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return;
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}
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issctrl_val |= ISS_CTRL_SYNC_DETECT_VS_RAISING;
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isp5ctrl_val |= ISP5_CTRL_VD_PULSE_EXT | ISP5_CTRL_PSYNC_CLK_SEL |
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ISP5_CTRL_SYNC_ENABLE;
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_CTRL, issctrl_val);
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, isp5ctrl_val);
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}
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#ifdef ISS_ISR_DEBUG
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static void iss_isr_dbg(struct iss_device *iss, u32 irqstatus)
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{
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static const char * const name[] = {
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"ISP_0",
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"ISP_1",
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"ISP_2",
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"ISP_3",
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"CSIA",
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"CSIB",
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"CCP2_0",
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"CCP2_1",
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"CCP2_2",
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"CCP2_3",
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"CBUFF",
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"BTE",
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"SIMCOP_0",
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"SIMCOP_1",
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"SIMCOP_2",
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"SIMCOP_3",
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"CCP2_8",
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"HS_VS",
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"18",
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"19",
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"20",
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"21",
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"22",
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"23",
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"24",
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"25",
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"26",
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"27",
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"28",
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"29",
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"30",
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"31",
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};
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unsigned int i;
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dev_dbg(iss->dev, "ISS IRQ: ");
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for (i = 0; i < ARRAY_SIZE(name); i++) {
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if ((1 << i) & irqstatus)
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pr_cont("%s ", name[i]);
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}
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pr_cont("\n");
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}
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static void iss_isp_isr_dbg(struct iss_device *iss, u32 irqstatus)
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{
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static const char * const name[] = {
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"ISIF_0",
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"ISIF_1",
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"ISIF_2",
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"ISIF_3",
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"IPIPEREQ",
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"IPIPELAST_PIX",
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"IPIPEDMA",
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"IPIPEBSC",
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"IPIPEHST",
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"IPIPEIF",
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"AEW",
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"AF",
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"H3A",
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"RSZ_REG",
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"RSZ_LAST_PIX",
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"RSZ_DMA",
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"RSZ_CYC_RZA",
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"RSZ_CYC_RZB",
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"RSZ_FIFO_OVF",
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"RSZ_FIFO_IN_BLK_ERR",
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"20",
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"21",
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"RSZ_EOF0",
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"RSZ_EOF1",
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"H3A_EOF",
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"IPIPE_EOF",
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"26",
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"IPIPE_DPC_INI",
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"IPIPE_DPC_RNEW0",
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"IPIPE_DPC_RNEW1",
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"30",
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"OCP_ERR",
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};
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unsigned int i;
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dev_dbg(iss->dev, "ISP IRQ: ");
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for (i = 0; i < ARRAY_SIZE(name); i++) {
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if ((1 << i) & irqstatus)
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pr_cont("%s ", name[i]);
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}
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pr_cont("\n");
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}
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#endif
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/*
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* iss_isr - Interrupt Service Routine for ISS module.
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* @irq: Not used currently.
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* @_iss: Pointer to the OMAP4 ISS device
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*
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* Handles the corresponding callback if plugged in.
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*
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* Returns IRQ_HANDLED when IRQ was correctly handled, or IRQ_NONE when the
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* IRQ wasn't handled.
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*/
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static irqreturn_t iss_isr(int irq, void *_iss)
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{
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static const u32 ipipeif_events = ISP5_IRQ_IPIPEIF_IRQ |
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ISP5_IRQ_ISIF_INT(0);
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static const u32 resizer_events = ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR |
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ISP5_IRQ_RSZ_FIFO_OVF |
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ISP5_IRQ_RSZ_INT_DMA;
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struct iss_device *iss = _iss;
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u32 irqstatus;
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irqstatus = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5));
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iss_reg_write(iss, OMAP4_ISS_MEM_TOP, ISS_HL_IRQSTATUS(5), irqstatus);
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if (irqstatus & ISS_HL_IRQ_CSIA)
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omap4iss_csi2_isr(&iss->csi2a);
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if (irqstatus & ISS_HL_IRQ_CSIB)
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omap4iss_csi2_isr(&iss->csi2b);
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if (irqstatus & ISS_HL_IRQ_ISP(0)) {
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u32 isp_irqstatus = iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1,
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ISP5_IRQSTATUS(0));
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iss_reg_write(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_IRQSTATUS(0),
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isp_irqstatus);
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if (isp_irqstatus & ISP5_IRQ_OCP_ERR)
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dev_dbg(iss->dev, "ISP5 OCP Error!\n");
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if (isp_irqstatus & ipipeif_events) {
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omap4iss_ipipeif_isr(&iss->ipipeif,
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isp_irqstatus & ipipeif_events);
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}
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if (isp_irqstatus & resizer_events)
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omap4iss_resizer_isr(&iss->resizer,
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isp_irqstatus & resizer_events);
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#ifdef ISS_ISR_DEBUG
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iss_isp_isr_dbg(iss, isp_irqstatus);
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#endif
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}
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omap4iss_flush(iss);
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#ifdef ISS_ISR_DEBUG
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iss_isr_dbg(iss, irqstatus);
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#endif
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return IRQ_HANDLED;
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}
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static const struct media_device_ops iss_media_ops = {
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.link_notify = v4l2_pipeline_link_notify,
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};
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/* -----------------------------------------------------------------------------
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* Pipeline stream management
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*/
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/*
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* iss_pipeline_disable - Disable streaming on a pipeline
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* @pipe: ISS pipeline
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* @until: entity at which to stop pipeline walk
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*
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* Walk the entities chain starting at the pipeline output video node and stop
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* all modules in the chain. Wait synchronously for the modules to be stopped if
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* necessary.
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*
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* If the until argument isn't NULL, stop the pipeline walk when reaching the
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* until entity. This is used to disable a partially started pipeline due to a
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* subdev start error.
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*/
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static int iss_pipeline_disable(struct iss_pipeline *pipe,
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struct media_entity *until)
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{
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struct iss_device *iss = pipe->output->iss;
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struct media_entity *entity;
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struct media_pad *pad;
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struct v4l2_subdev *subdev;
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int failure = 0;
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int ret;
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entity = &pipe->output->video.entity;
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while (1) {
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pad = &entity->pads[0];
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if (!(pad->flags & MEDIA_PAD_FL_SINK))
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break;
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pad = media_entity_remote_pad(pad);
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if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
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break;
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entity = pad->entity;
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if (entity == until)
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break;
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subdev = media_entity_to_v4l2_subdev(entity);
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ret = v4l2_subdev_call(subdev, video, s_stream, 0);
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if (ret < 0) {
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dev_warn(iss->dev, "%s: module stop timeout.\n",
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subdev->name);
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/* If the entity failed to stopped, assume it has
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* crashed. Mark it as such, the ISS will be reset when
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* applications will release it.
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*/
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media_entity_enum_set(&iss->crashed, &subdev->entity);
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failure = -ETIMEDOUT;
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}
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}
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return failure;
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}
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/*
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* iss_pipeline_enable - Enable streaming on a pipeline
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* @pipe: ISS pipeline
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* @mode: Stream mode (single shot or continuous)
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*
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* Walk the entities chain starting at the pipeline output video node and start
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* all modules in the chain in the given mode.
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*
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* Return 0 if successful, or the return value of the failed video::s_stream
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* operation otherwise.
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*/
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static int iss_pipeline_enable(struct iss_pipeline *pipe,
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enum iss_pipeline_stream_state mode)
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{
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struct iss_device *iss = pipe->output->iss;
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struct media_entity *entity;
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struct media_pad *pad;
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struct v4l2_subdev *subdev;
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unsigned long flags;
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int ret;
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/* If one of the entities in the pipeline has crashed it will not work
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* properly. Refuse to start streaming in that case. This check must be
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* performed before the loop below to avoid starting entities if the
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* pipeline won't start anyway (those entities would then likely fail to
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* stop, making the problem worse).
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*/
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if (media_entity_enum_intersects(&pipe->ent_enum, &iss->crashed))
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return -EIO;
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spin_lock_irqsave(&pipe->lock, flags);
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pipe->state &= ~(ISS_PIPELINE_IDLE_INPUT | ISS_PIPELINE_IDLE_OUTPUT);
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spin_unlock_irqrestore(&pipe->lock, flags);
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pipe->do_propagation = false;
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entity = &pipe->output->video.entity;
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while (1) {
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pad = &entity->pads[0];
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if (!(pad->flags & MEDIA_PAD_FL_SINK))
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break;
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pad = media_entity_remote_pad(pad);
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if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
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break;
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entity = pad->entity;
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subdev = media_entity_to_v4l2_subdev(entity);
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ret = v4l2_subdev_call(subdev, video, s_stream, mode);
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if (ret < 0 && ret != -ENOIOCTLCMD) {
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iss_pipeline_disable(pipe, entity);
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return ret;
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}
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if (subdev == &iss->csi2a.subdev ||
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subdev == &iss->csi2b.subdev)
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pipe->do_propagation = true;
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}
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iss_print_status(pipe->output->iss);
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return 0;
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}
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/*
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* omap4iss_pipeline_set_stream - Enable/disable streaming on a pipeline
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* @pipe: ISS pipeline
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* @state: Stream state (stopped, single shot or continuous)
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*
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* Set the pipeline to the given stream state. Pipelines can be started in
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* single-shot or continuous mode.
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*
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* Return 0 if successful, or the return value of the failed video::s_stream
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* operation otherwise. The pipeline state is not updated when the operation
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* fails, except when stopping the pipeline.
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*/
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int omap4iss_pipeline_set_stream(struct iss_pipeline *pipe,
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enum iss_pipeline_stream_state state)
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{
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int ret;
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if (state == ISS_PIPELINE_STREAM_STOPPED)
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ret = iss_pipeline_disable(pipe, NULL);
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else
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ret = iss_pipeline_enable(pipe, state);
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if (ret == 0 || state == ISS_PIPELINE_STREAM_STOPPED)
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pipe->stream_state = state;
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return ret;
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}
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/*
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* omap4iss_pipeline_cancel_stream - Cancel stream on a pipeline
|
* @pipe: ISS pipeline
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*
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* Cancelling a stream mark all buffers on all video nodes in the pipeline as
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* erroneous and makes sure no new buffer can be queued. This function is called
|
* when a fatal error that prevents any further operation on the pipeline
|
* occurs.
|
*/
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void omap4iss_pipeline_cancel_stream(struct iss_pipeline *pipe)
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{
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if (pipe->input)
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omap4iss_video_cancel_stream(pipe->input);
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if (pipe->output)
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omap4iss_video_cancel_stream(pipe->output);
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}
|
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/*
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* iss_pipeline_is_last - Verify if entity has an enabled link to the output
|
* video node
|
* @me: ISS module's media entity
|
*
|
* Returns 1 if the entity has an enabled link to the output video node or 0
|
* otherwise. It's true only while pipeline can have no more than one output
|
* node.
|
*/
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static int iss_pipeline_is_last(struct media_entity *me)
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{
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struct iss_pipeline *pipe;
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struct media_pad *pad;
|
|
if (!me->pipe)
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return 0;
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pipe = to_iss_pipeline(me);
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if (pipe->stream_state == ISS_PIPELINE_STREAM_STOPPED)
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return 0;
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pad = media_entity_remote_pad(&pipe->output->pad);
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return pad->entity == me;
|
}
|
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static int iss_reset(struct iss_device *iss)
|
{
|
unsigned int timeout;
|
|
iss_reg_set(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG,
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ISS_HL_SYSCONFIG_SOFTRESET);
|
|
timeout = iss_poll_condition_timeout(
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!(iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_SYSCONFIG) &
|
ISS_HL_SYSCONFIG_SOFTRESET), 1000, 10, 100);
|
if (timeout) {
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dev_err(iss->dev, "ISS reset timeout\n");
|
return -ETIMEDOUT;
|
}
|
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media_entity_enum_zero(&iss->crashed);
|
|
return 0;
|
}
|
|
static int iss_isp_reset(struct iss_device *iss)
|
{
|
unsigned int timeout;
|
|
/* Fist, ensure that the ISP is IDLE (no transactions happening) */
|
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG,
|
ISP5_SYSCONFIG_STANDBYMODE_MASK,
|
ISP5_SYSCONFIG_STANDBYMODE_SMART);
|
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iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL, ISP5_CTRL_MSTANDBY);
|
|
timeout = iss_poll_condition_timeout(
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iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL) &
|
ISP5_CTRL_MSTANDBY_WAIT, 1000000, 1000, 1500);
|
if (timeout) {
|
dev_err(iss->dev, "ISP5 standby timeout\n");
|
return -ETIMEDOUT;
|
}
|
|
/* Now finally, do the reset */
|
iss_reg_set(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG,
|
ISP5_SYSCONFIG_SOFTRESET);
|
|
timeout = iss_poll_condition_timeout(
|
!(iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_SYSCONFIG) &
|
ISP5_SYSCONFIG_SOFTRESET), 1000000, 1000, 1500);
|
if (timeout) {
|
dev_err(iss->dev, "ISP5 reset timeout\n");
|
return -ETIMEDOUT;
|
}
|
|
return 0;
|
}
|
|
/*
|
* iss_module_sync_idle - Helper to sync module with its idle state
|
* @me: ISS submodule's media entity
|
* @wait: ISS submodule's wait queue for streamoff/interrupt synchronization
|
* @stopping: flag which tells module wants to stop
|
*
|
* This function checks if ISS submodule needs to wait for next interrupt. If
|
* yes, makes the caller to sleep while waiting for such event.
|
*/
|
int omap4iss_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
|
atomic_t *stopping)
|
{
|
struct iss_pipeline *pipe = to_iss_pipeline(me);
|
struct iss_video *video = pipe->output;
|
unsigned long flags;
|
|
if (pipe->stream_state == ISS_PIPELINE_STREAM_STOPPED ||
|
(pipe->stream_state == ISS_PIPELINE_STREAM_SINGLESHOT &&
|
!iss_pipeline_ready(pipe)))
|
return 0;
|
|
/*
|
* atomic_set() doesn't include memory barrier on ARM platform for SMP
|
* scenario. We'll call it here to avoid race conditions.
|
*/
|
atomic_set(stopping, 1);
|
smp_wmb();
|
|
/*
|
* If module is the last one, it's writing to memory. In this case,
|
* it's necessary to check if the module is already paused due to
|
* DMA queue underrun or if it has to wait for next interrupt to be
|
* idle.
|
* If it isn't the last one, the function won't sleep but *stopping
|
* will still be set to warn next submodule caller's interrupt the
|
* module wants to be idle.
|
*/
|
if (!iss_pipeline_is_last(me))
|
return 0;
|
|
spin_lock_irqsave(&video->qlock, flags);
|
if (video->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) {
|
spin_unlock_irqrestore(&video->qlock, flags);
|
atomic_set(stopping, 0);
|
smp_wmb();
|
return 0;
|
}
|
spin_unlock_irqrestore(&video->qlock, flags);
|
if (!wait_event_timeout(*wait, !atomic_read(stopping),
|
msecs_to_jiffies(1000))) {
|
atomic_set(stopping, 0);
|
smp_wmb();
|
return -ETIMEDOUT;
|
}
|
|
return 0;
|
}
|
|
/*
|
* omap4iss_module_sync_is_stopped - Helper to verify if module was stopping
|
* @wait: ISS submodule's wait queue for streamoff/interrupt synchronization
|
* @stopping: flag which tells module wants to stop
|
*
|
* This function checks if ISS submodule was stopping. In case of yes, it
|
* notices the caller by setting stopping to 0 and waking up the wait queue.
|
* Returns 1 if it was stopping or 0 otherwise.
|
*/
|
int omap4iss_module_sync_is_stopping(wait_queue_head_t *wait,
|
atomic_t *stopping)
|
{
|
if (atomic_cmpxchg(stopping, 1, 0)) {
|
wake_up(wait);
|
return 1;
|
}
|
|
return 0;
|
}
|
|
/* --------------------------------------------------------------------------
|
* Clock management
|
*/
|
|
#define ISS_CLKCTRL_MASK (ISS_CLKCTRL_CSI2_A |\
|
ISS_CLKCTRL_CSI2_B |\
|
ISS_CLKCTRL_ISP)
|
|
static int __iss_subclk_update(struct iss_device *iss)
|
{
|
u32 clk = 0;
|
int ret = 0, timeout = 1000;
|
|
if (iss->subclk_resources & OMAP4_ISS_SUBCLK_CSI2_A)
|
clk |= ISS_CLKCTRL_CSI2_A;
|
|
if (iss->subclk_resources & OMAP4_ISS_SUBCLK_CSI2_B)
|
clk |= ISS_CLKCTRL_CSI2_B;
|
|
if (iss->subclk_resources & OMAP4_ISS_SUBCLK_ISP)
|
clk |= ISS_CLKCTRL_ISP;
|
|
iss_reg_update(iss, OMAP4_ISS_MEM_TOP, ISS_CLKCTRL,
|
ISS_CLKCTRL_MASK, clk);
|
|
/* Wait for HW assertion */
|
while (--timeout > 0) {
|
udelay(1);
|
if ((iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_CLKSTAT) &
|
ISS_CLKCTRL_MASK) == clk)
|
break;
|
}
|
|
if (!timeout)
|
ret = -EBUSY;
|
|
return ret;
|
}
|
|
int omap4iss_subclk_enable(struct iss_device *iss,
|
enum iss_subclk_resource res)
|
{
|
iss->subclk_resources |= res;
|
|
return __iss_subclk_update(iss);
|
}
|
|
int omap4iss_subclk_disable(struct iss_device *iss,
|
enum iss_subclk_resource res)
|
{
|
iss->subclk_resources &= ~res;
|
|
return __iss_subclk_update(iss);
|
}
|
|
#define ISS_ISP5_CLKCTRL_MASK (ISP5_CTRL_BL_CLK_ENABLE |\
|
ISP5_CTRL_ISIF_CLK_ENABLE |\
|
ISP5_CTRL_H3A_CLK_ENABLE |\
|
ISP5_CTRL_RSZ_CLK_ENABLE |\
|
ISP5_CTRL_IPIPE_CLK_ENABLE |\
|
ISP5_CTRL_IPIPEIF_CLK_ENABLE)
|
|
static void __iss_isp_subclk_update(struct iss_device *iss)
|
{
|
u32 clk = 0;
|
|
if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_ISIF)
|
clk |= ISP5_CTRL_ISIF_CLK_ENABLE;
|
|
if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_H3A)
|
clk |= ISP5_CTRL_H3A_CLK_ENABLE;
|
|
if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_RSZ)
|
clk |= ISP5_CTRL_RSZ_CLK_ENABLE;
|
|
if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_IPIPE)
|
clk |= ISP5_CTRL_IPIPE_CLK_ENABLE;
|
|
if (iss->isp_subclk_resources & OMAP4_ISS_ISP_SUBCLK_IPIPEIF)
|
clk |= ISP5_CTRL_IPIPEIF_CLK_ENABLE;
|
|
if (clk)
|
clk |= ISP5_CTRL_BL_CLK_ENABLE;
|
|
iss_reg_update(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_CTRL,
|
ISS_ISP5_CLKCTRL_MASK, clk);
|
}
|
|
void omap4iss_isp_subclk_enable(struct iss_device *iss,
|
enum iss_isp_subclk_resource res)
|
{
|
iss->isp_subclk_resources |= res;
|
|
__iss_isp_subclk_update(iss);
|
}
|
|
void omap4iss_isp_subclk_disable(struct iss_device *iss,
|
enum iss_isp_subclk_resource res)
|
{
|
iss->isp_subclk_resources &= ~res;
|
|
__iss_isp_subclk_update(iss);
|
}
|
|
/*
|
* iss_enable_clocks - Enable ISS clocks
|
* @iss: OMAP4 ISS device
|
*
|
* Return 0 if successful, or clk_enable return value if any of tthem fails.
|
*/
|
static int iss_enable_clocks(struct iss_device *iss)
|
{
|
int ret;
|
|
ret = clk_enable(iss->iss_fck);
|
if (ret) {
|
dev_err(iss->dev, "clk_enable iss_fck failed\n");
|
return ret;
|
}
|
|
ret = clk_enable(iss->iss_ctrlclk);
|
if (ret) {
|
dev_err(iss->dev, "clk_enable iss_ctrlclk failed\n");
|
clk_disable(iss->iss_fck);
|
return ret;
|
}
|
|
return 0;
|
}
|
|
/*
|
* iss_disable_clocks - Disable ISS clocks
|
* @iss: OMAP4 ISS device
|
*/
|
static void iss_disable_clocks(struct iss_device *iss)
|
{
|
clk_disable(iss->iss_ctrlclk);
|
clk_disable(iss->iss_fck);
|
}
|
|
static int iss_get_clocks(struct iss_device *iss)
|
{
|
iss->iss_fck = devm_clk_get(iss->dev, "iss_fck");
|
if (IS_ERR(iss->iss_fck)) {
|
dev_err(iss->dev, "Unable to get iss_fck clock info\n");
|
return PTR_ERR(iss->iss_fck);
|
}
|
|
iss->iss_ctrlclk = devm_clk_get(iss->dev, "iss_ctrlclk");
|
if (IS_ERR(iss->iss_ctrlclk)) {
|
dev_err(iss->dev, "Unable to get iss_ctrlclk clock info\n");
|
return PTR_ERR(iss->iss_ctrlclk);
|
}
|
|
return 0;
|
}
|
|
/*
|
* omap4iss_get - Acquire the ISS resource.
|
*
|
* Initializes the clocks for the first acquire.
|
*
|
* Increment the reference count on the ISS. If the first reference is taken,
|
* enable clocks and power-up all submodules.
|
*
|
* Return a pointer to the ISS device structure, or NULL if an error occurred.
|
*/
|
struct iss_device *omap4iss_get(struct iss_device *iss)
|
{
|
struct iss_device *__iss = iss;
|
|
if (!iss)
|
return NULL;
|
|
mutex_lock(&iss->iss_mutex);
|
if (iss->ref_count > 0)
|
goto out;
|
|
if (iss_enable_clocks(iss) < 0) {
|
__iss = NULL;
|
goto out;
|
}
|
|
iss_enable_interrupts(iss);
|
|
out:
|
if (__iss)
|
iss->ref_count++;
|
mutex_unlock(&iss->iss_mutex);
|
|
return __iss;
|
}
|
|
/*
|
* omap4iss_put - Release the ISS
|
*
|
* Decrement the reference count on the ISS. If the last reference is released,
|
* power-down all submodules, disable clocks and free temporary buffers.
|
*/
|
void omap4iss_put(struct iss_device *iss)
|
{
|
if (!iss)
|
return;
|
|
mutex_lock(&iss->iss_mutex);
|
WARN_ON(iss->ref_count == 0);
|
if (--iss->ref_count == 0) {
|
iss_disable_interrupts(iss);
|
/* Reset the ISS if an entity has failed to stop. This is the
|
* only way to recover from such conditions, although it would
|
* be worth investigating whether resetting the ISP only can't
|
* fix the problem in some cases.
|
*/
|
if (!media_entity_enum_empty(&iss->crashed))
|
iss_reset(iss);
|
iss_disable_clocks(iss);
|
}
|
mutex_unlock(&iss->iss_mutex);
|
}
|
|
static int iss_map_mem_resource(struct platform_device *pdev,
|
struct iss_device *iss,
|
enum iss_mem_resources res)
|
{
|
iss->regs[res] = devm_platform_ioremap_resource(pdev, res);
|
|
return PTR_ERR_OR_ZERO(iss->regs[res]);
|
}
|
|
static void iss_unregister_entities(struct iss_device *iss)
|
{
|
omap4iss_resizer_unregister_entities(&iss->resizer);
|
omap4iss_ipipe_unregister_entities(&iss->ipipe);
|
omap4iss_ipipeif_unregister_entities(&iss->ipipeif);
|
omap4iss_csi2_unregister_entities(&iss->csi2a);
|
omap4iss_csi2_unregister_entities(&iss->csi2b);
|
|
v4l2_device_unregister(&iss->v4l2_dev);
|
media_device_unregister(&iss->media_dev);
|
}
|
|
/*
|
* iss_register_subdev_group - Register a group of subdevices
|
* @iss: OMAP4 ISS device
|
* @board_info: I2C subdevs board information array
|
*
|
* Register all I2C subdevices in the board_info array. The array must be
|
* terminated by a NULL entry, and the first entry must be the sensor.
|
*
|
* Return a pointer to the sensor media entity if it has been successfully
|
* registered, or NULL otherwise.
|
*/
|
static struct v4l2_subdev *
|
iss_register_subdev_group(struct iss_device *iss,
|
struct iss_subdev_i2c_board_info *board_info)
|
{
|
struct v4l2_subdev *sensor = NULL;
|
unsigned int first;
|
|
if (!board_info->board_info)
|
return NULL;
|
|
for (first = 1; board_info->board_info; ++board_info, first = 0) {
|
struct v4l2_subdev *subdev;
|
struct i2c_adapter *adapter;
|
|
adapter = i2c_get_adapter(board_info->i2c_adapter_id);
|
if (!adapter) {
|
dev_err(iss->dev,
|
"%s: Unable to get I2C adapter %d for device %s\n",
|
__func__, board_info->i2c_adapter_id,
|
board_info->board_info->type);
|
continue;
|
}
|
|
subdev = v4l2_i2c_new_subdev_board(&iss->v4l2_dev, adapter,
|
board_info->board_info, NULL);
|
if (!subdev) {
|
dev_err(iss->dev, "Unable to register subdev %s\n",
|
board_info->board_info->type);
|
continue;
|
}
|
|
if (first)
|
sensor = subdev;
|
}
|
|
return sensor;
|
}
|
|
static int iss_register_entities(struct iss_device *iss)
|
{
|
struct iss_platform_data *pdata = iss->pdata;
|
struct iss_v4l2_subdevs_group *subdevs;
|
int ret;
|
|
iss->media_dev.dev = iss->dev;
|
strscpy(iss->media_dev.model, "TI OMAP4 ISS",
|
sizeof(iss->media_dev.model));
|
iss->media_dev.hw_revision = iss->revision;
|
iss->media_dev.ops = &iss_media_ops;
|
ret = media_device_register(&iss->media_dev);
|
if (ret < 0) {
|
dev_err(iss->dev, "Media device registration failed (%d)\n",
|
ret);
|
return ret;
|
}
|
|
iss->v4l2_dev.mdev = &iss->media_dev;
|
ret = v4l2_device_register(iss->dev, &iss->v4l2_dev);
|
if (ret < 0) {
|
dev_err(iss->dev, "V4L2 device registration failed (%d)\n",
|
ret);
|
goto done;
|
}
|
|
/* Register internal entities */
|
ret = omap4iss_csi2_register_entities(&iss->csi2a, &iss->v4l2_dev);
|
if (ret < 0)
|
goto done;
|
|
ret = omap4iss_csi2_register_entities(&iss->csi2b, &iss->v4l2_dev);
|
if (ret < 0)
|
goto done;
|
|
ret = omap4iss_ipipeif_register_entities(&iss->ipipeif, &iss->v4l2_dev);
|
if (ret < 0)
|
goto done;
|
|
ret = omap4iss_ipipe_register_entities(&iss->ipipe, &iss->v4l2_dev);
|
if (ret < 0)
|
goto done;
|
|
ret = omap4iss_resizer_register_entities(&iss->resizer, &iss->v4l2_dev);
|
if (ret < 0)
|
goto done;
|
|
/* Register external entities */
|
for (subdevs = pdata->subdevs; subdevs && subdevs->subdevs; ++subdevs) {
|
struct v4l2_subdev *sensor;
|
struct media_entity *input;
|
unsigned int flags;
|
unsigned int pad;
|
|
sensor = iss_register_subdev_group(iss, subdevs->subdevs);
|
if (!sensor)
|
continue;
|
|
sensor->host_priv = subdevs;
|
|
/* Connect the sensor to the correct interface module.
|
* CSI2a receiver through CSIPHY1, or
|
* CSI2b receiver through CSIPHY2
|
*/
|
switch (subdevs->interface) {
|
case ISS_INTERFACE_CSI2A_PHY1:
|
input = &iss->csi2a.subdev.entity;
|
pad = CSI2_PAD_SINK;
|
flags = MEDIA_LNK_FL_IMMUTABLE
|
| MEDIA_LNK_FL_ENABLED;
|
break;
|
|
case ISS_INTERFACE_CSI2B_PHY2:
|
input = &iss->csi2b.subdev.entity;
|
pad = CSI2_PAD_SINK;
|
flags = MEDIA_LNK_FL_IMMUTABLE
|
| MEDIA_LNK_FL_ENABLED;
|
break;
|
|
default:
|
dev_err(iss->dev, "invalid interface type %u\n",
|
subdevs->interface);
|
ret = -EINVAL;
|
goto done;
|
}
|
|
ret = media_create_pad_link(&sensor->entity, 0, input, pad,
|
flags);
|
if (ret < 0)
|
goto done;
|
}
|
|
ret = v4l2_device_register_subdev_nodes(&iss->v4l2_dev);
|
|
done:
|
if (ret < 0)
|
iss_unregister_entities(iss);
|
|
return ret;
|
}
|
|
/*
|
* iss_create_links() - Pads links creation for the subdevices
|
* @iss : Pointer to ISS device
|
*
|
* return negative error code or zero on success
|
*/
|
static int iss_create_links(struct iss_device *iss)
|
{
|
int ret;
|
|
ret = omap4iss_csi2_create_links(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "CSI2 pads links creation failed\n");
|
return ret;
|
}
|
|
ret = omap4iss_ipipeif_create_links(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "ISP IPIPEIF pads links creation failed\n");
|
return ret;
|
}
|
|
ret = omap4iss_resizer_create_links(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "ISP RESIZER pads links creation failed\n");
|
return ret;
|
}
|
|
/* Connect the submodules. */
|
ret = media_create_pad_link(
|
&iss->csi2a.subdev.entity, CSI2_PAD_SOURCE,
|
&iss->ipipeif.subdev.entity, IPIPEIF_PAD_SINK, 0);
|
if (ret < 0)
|
return ret;
|
|
ret = media_create_pad_link(
|
&iss->csi2b.subdev.entity, CSI2_PAD_SOURCE,
|
&iss->ipipeif.subdev.entity, IPIPEIF_PAD_SINK, 0);
|
if (ret < 0)
|
return ret;
|
|
ret = media_create_pad_link(
|
&iss->ipipeif.subdev.entity, IPIPEIF_PAD_SOURCE_VP,
|
&iss->resizer.subdev.entity, RESIZER_PAD_SINK, 0);
|
if (ret < 0)
|
return ret;
|
|
ret = media_create_pad_link(
|
&iss->ipipeif.subdev.entity, IPIPEIF_PAD_SOURCE_VP,
|
&iss->ipipe.subdev.entity, IPIPE_PAD_SINK, 0);
|
if (ret < 0)
|
return ret;
|
|
ret = media_create_pad_link(
|
&iss->ipipe.subdev.entity, IPIPE_PAD_SOURCE_VP,
|
&iss->resizer.subdev.entity, RESIZER_PAD_SINK, 0);
|
if (ret < 0)
|
return ret;
|
|
return 0;
|
};
|
|
static void iss_cleanup_modules(struct iss_device *iss)
|
{
|
omap4iss_csi2_cleanup(iss);
|
omap4iss_ipipeif_cleanup(iss);
|
omap4iss_ipipe_cleanup(iss);
|
omap4iss_resizer_cleanup(iss);
|
}
|
|
static int iss_initialize_modules(struct iss_device *iss)
|
{
|
int ret;
|
|
ret = omap4iss_csiphy_init(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "CSI PHY initialization failed\n");
|
goto error_csiphy;
|
}
|
|
ret = omap4iss_csi2_init(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "CSI2 initialization failed\n");
|
goto error_csi2;
|
}
|
|
ret = omap4iss_ipipeif_init(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "ISP IPIPEIF initialization failed\n");
|
goto error_ipipeif;
|
}
|
|
ret = omap4iss_ipipe_init(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "ISP IPIPE initialization failed\n");
|
goto error_ipipe;
|
}
|
|
ret = omap4iss_resizer_init(iss);
|
if (ret < 0) {
|
dev_err(iss->dev, "ISP RESIZER initialization failed\n");
|
goto error_resizer;
|
}
|
|
return 0;
|
|
error_resizer:
|
omap4iss_ipipe_cleanup(iss);
|
error_ipipe:
|
omap4iss_ipipeif_cleanup(iss);
|
error_ipipeif:
|
omap4iss_csi2_cleanup(iss);
|
error_csi2:
|
error_csiphy:
|
return ret;
|
}
|
|
static int iss_probe(struct platform_device *pdev)
|
{
|
struct iss_platform_data *pdata = pdev->dev.platform_data;
|
struct iss_device *iss;
|
unsigned int i;
|
int ret;
|
|
if (!pdata)
|
return -EINVAL;
|
|
iss = devm_kzalloc(&pdev->dev, sizeof(*iss), GFP_KERNEL);
|
if (!iss)
|
return -ENOMEM;
|
|
mutex_init(&iss->iss_mutex);
|
|
iss->dev = &pdev->dev;
|
iss->pdata = pdata;
|
|
iss->raw_dmamask = DMA_BIT_MASK(32);
|
iss->dev->dma_mask = &iss->raw_dmamask;
|
iss->dev->coherent_dma_mask = DMA_BIT_MASK(32);
|
|
platform_set_drvdata(pdev, iss);
|
|
/*
|
* TODO: When implementing DT support switch to syscon regmap lookup by
|
* phandle.
|
*/
|
iss->syscon = syscon_regmap_lookup_by_compatible("syscon");
|
if (IS_ERR(iss->syscon)) {
|
ret = PTR_ERR(iss->syscon);
|
goto error;
|
}
|
|
/* Clocks */
|
ret = iss_map_mem_resource(pdev, iss, OMAP4_ISS_MEM_TOP);
|
if (ret < 0)
|
goto error;
|
|
ret = iss_get_clocks(iss);
|
if (ret < 0)
|
goto error;
|
|
if (!omap4iss_get(iss)) {
|
ret = -EINVAL;
|
goto error;
|
}
|
|
ret = iss_reset(iss);
|
if (ret < 0)
|
goto error_iss;
|
|
iss->revision = iss_reg_read(iss, OMAP4_ISS_MEM_TOP, ISS_HL_REVISION);
|
dev_info(iss->dev, "Revision %08x found\n", iss->revision);
|
|
for (i = 1; i < OMAP4_ISS_MEM_LAST; i++) {
|
ret = iss_map_mem_resource(pdev, iss, i);
|
if (ret)
|
goto error_iss;
|
}
|
|
/* Configure BTE BW_LIMITER field to max recommended value (1 GB) */
|
iss_reg_update(iss, OMAP4_ISS_MEM_BTE, BTE_CTRL,
|
BTE_CTRL_BW_LIMITER_MASK,
|
18 << BTE_CTRL_BW_LIMITER_SHIFT);
|
|
/* Perform ISP reset */
|
ret = omap4iss_subclk_enable(iss, OMAP4_ISS_SUBCLK_ISP);
|
if (ret < 0)
|
goto error_iss;
|
|
ret = iss_isp_reset(iss);
|
if (ret < 0)
|
goto error_iss;
|
|
dev_info(iss->dev, "ISP Revision %08x found\n",
|
iss_reg_read(iss, OMAP4_ISS_MEM_ISP_SYS1, ISP5_REVISION));
|
|
/* Interrupt */
|
ret = platform_get_irq(pdev, 0);
|
if (ret <= 0) {
|
ret = -ENODEV;
|
goto error_iss;
|
}
|
iss->irq_num = ret;
|
|
if (devm_request_irq(iss->dev, iss->irq_num, iss_isr, IRQF_SHARED,
|
"OMAP4 ISS", iss)) {
|
dev_err(iss->dev, "Unable to request IRQ\n");
|
ret = -EINVAL;
|
goto error_iss;
|
}
|
|
/* Entities */
|
ret = iss_initialize_modules(iss);
|
if (ret < 0)
|
goto error_iss;
|
|
ret = iss_register_entities(iss);
|
if (ret < 0)
|
goto error_modules;
|
|
ret = media_entity_enum_init(&iss->crashed, &iss->media_dev);
|
if (ret)
|
goto error_entities;
|
|
ret = iss_create_links(iss);
|
if (ret < 0)
|
goto error_entities;
|
|
omap4iss_put(iss);
|
|
return 0;
|
|
error_entities:
|
iss_unregister_entities(iss);
|
media_entity_enum_cleanup(&iss->crashed);
|
error_modules:
|
iss_cleanup_modules(iss);
|
error_iss:
|
omap4iss_put(iss);
|
error:
|
mutex_destroy(&iss->iss_mutex);
|
|
return ret;
|
}
|
|
static int iss_remove(struct platform_device *pdev)
|
{
|
struct iss_device *iss = platform_get_drvdata(pdev);
|
|
iss_unregister_entities(iss);
|
media_entity_enum_cleanup(&iss->crashed);
|
iss_cleanup_modules(iss);
|
|
return 0;
|
}
|
|
static const struct platform_device_id omap4iss_id_table[] = {
|
{ "omap4iss", 0 },
|
{ },
|
};
|
MODULE_DEVICE_TABLE(platform, omap4iss_id_table);
|
|
static struct platform_driver iss_driver = {
|
.probe = iss_probe,
|
.remove = iss_remove,
|
.id_table = omap4iss_id_table,
|
.driver = {
|
.name = "omap4iss",
|
},
|
};
|
|
module_platform_driver(iss_driver);
|
|
MODULE_DESCRIPTION("TI OMAP4 ISS driver");
|
MODULE_AUTHOR("Sergio Aguirre <sergio.a.aguirre@gmail.com>");
|
MODULE_LICENSE("GPL");
|
MODULE_VERSION(ISS_VIDEO_DRIVER_VERSION);
|
