/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* EMXX FCD (Function Controller Driver) for USB.
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*
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* Copyright (C) 2010 Renesas Electronics Corporation
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*/
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#ifndef _LINUX_EMXX_H
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#define _LINUX_EMXX_H
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/*---------------------------------------------------------------------------*/
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/*----------------- Default define */
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#define USE_DMA 1
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#define USE_SUSPEND_WAIT 1
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/*------------ Board dependence(Resource) */
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#define VBUS_VALUE GPIO_VBUS
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/* below hacked up for staging integration */
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#define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
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#define INT_VBUS 0 /* IRQ for GPIO_P153 */
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struct gpio_desc *vbus_gpio;
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int vbus_irq;
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/*------------ Board dependence(Wait) */
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/* CHATTERING wait time ms */
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#define VBUS_CHATTERING_MDELAY 1
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/* DMA Abort wait time ms */
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#define DMA_DISABLE_TIME 10
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/*------------ Controller dependence */
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#define NUM_ENDPOINTS 14 /* Endpoint */
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#define REG_EP_NUM 15 /* Endpoint Register */
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#define DMA_MAX_COUNT 256 /* DMA Block */
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#define EPC_RST_DISABLE_TIME 1 /* 1 usec */
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#define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */
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#define EPC_PLL_LOCK_COUNT 1000 /* 1000 */
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#define IN_DATA_EMPTY_COUNT 1000 /* 1000 */
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#define CHATGER_TIME 700 /* 700msec */
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#define USB_SUSPEND_TIME 2000 /* 2 sec */
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/* U2F FLAG */
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#define U2F_ENABLE 1
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#define U2F_DISABLE 0
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#define TEST_FORCE_ENABLE (BIT(18) | BIT(16))
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#define INT_SEL BIT(10)
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#define CONSTFS BIT(9)
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#define SOF_RCV BIT(8)
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#define RSUM_IN BIT(7)
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#define SUSPEND BIT(6)
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#define CONF BIT(5)
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#define DEFAULT BIT(4)
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#define CONNECTB BIT(3)
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#define PUE2 BIT(2)
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#define MAX_TEST_MODE_NUM 0x05
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#define TEST_MODE_SHIFT 16
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/*------- (0x0004) USB Status Register */
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#define SPEED_MODE BIT(6)
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#define HIGH_SPEED BIT(6)
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#define CONF BIT(5)
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#define DEFAULT BIT(4)
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#define USB_RST BIT(3)
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#define SPND_OUT BIT(2)
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#define RSUM_OUT BIT(1)
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/*------- (0x0008) USB Address Register */
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#define USB_ADDR 0x007F0000
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#define SOF_STATUS BIT(15)
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#define UFRAME (BIT(14) | BIT(13) | BIT(12))
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#define FRAME 0x000007FF
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#define USB_ADRS_SHIFT 16
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/*------- (0x000C) UTMI Characteristic 1 Register */
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#define SQUSET (BIT(7) | BIT(6) | BIT(5) | BIT(4))
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#define USB_SQUSET (BIT(6) | BIT(5) | BIT(4))
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/*------- (0x0010) TEST Control Register */
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#define FORCEHS BIT(2)
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#define CS_TESTMODEEN BIT(1)
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#define LOOPBACK BIT(0)
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/*------- (0x0018) Setup Data 0 Register */
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/*------- (0x001C) Setup Data 1 Register */
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/*------- (0x0020) USB Interrupt Status Register */
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#define EPN_INT 0x00FFFF00
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#define EP15_INT BIT(23)
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#define EP14_INT BIT(22)
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#define EP13_INT BIT(21)
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#define EP12_INT BIT(20)
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#define EP11_INT BIT(19)
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#define EP10_INT BIT(18)
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#define EP9_INT BIT(17)
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#define EP8_INT BIT(16)
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#define EP7_INT BIT(15)
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#define EP6_INT BIT(14)
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#define EP5_INT BIT(13)
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#define EP4_INT BIT(12)
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#define EP3_INT BIT(11)
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#define EP2_INT BIT(10)
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#define EP1_INT BIT(9)
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#define EP0_INT BIT(8)
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#define SPEED_MODE_INT BIT(6)
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#define SOF_ERROR_INT BIT(5)
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#define SOF_INT BIT(4)
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#define USB_RST_INT BIT(3)
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#define SPND_INT BIT(2)
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#define RSUM_INT BIT(1)
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#define USB_INT_STA_RW 0x7E
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/*------- (0x0024) USB Interrupt Enable Register */
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#define EP15_0_EN 0x00FFFF00
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#define EP15_EN BIT(23)
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#define EP14_EN BIT(22)
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#define EP13_EN BIT(21)
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#define EP12_EN BIT(20)
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#define EP11_EN BIT(19)
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#define EP10_EN BIT(18)
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#define EP9_EN BIT(17)
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#define EP8_EN BIT(16)
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#define EP7_EN BIT(15)
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#define EP6_EN BIT(14)
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#define EP5_EN BIT(13)
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#define EP4_EN BIT(12)
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#define EP3_EN BIT(11)
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#define EP2_EN BIT(10)
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#define EP1_EN BIT(9)
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#define EP0_EN BIT(8)
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#define SPEED_MODE_EN BIT(6)
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#define SOF_ERROR_EN BIT(5)
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#define SOF_EN BIT(4)
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#define USB_RST_EN BIT(3)
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#define SPND_EN BIT(2)
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#define RSUM_EN BIT(1)
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#define USB_INT_EN_BIT \
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(EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN)
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/*------- (0x0028) EP0 Control Register */
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#define EP0_STGSEL BIT(18)
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#define EP0_OVERSEL BIT(17)
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#define EP0_AUTO BIT(16)
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#define EP0_PIDCLR BIT(9)
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#define EP0_BCLR BIT(8)
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#define EP0_DEND BIT(7)
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#define EP0_DW (BIT(6) | BIT(5))
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#define EP0_DW4 0
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#define EP0_DW3 (BIT(6) | BIT(5))
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#define EP0_DW2 BIT(6)
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#define EP0_DW1 BIT(5)
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#define EP0_INAK_EN BIT(4)
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#define EP0_PERR_NAK_CLR BIT(3)
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#define EP0_STL BIT(2)
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#define EP0_INAK BIT(1)
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#define EP0_ONAK BIT(0)
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/*------- (0x002C) EP0 Status Register */
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#define EP0_PID BIT(18)
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#define EP0_PERR_NAK BIT(17)
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#define EP0_PERR_NAK_INT BIT(16)
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#define EP0_OUT_NAK_INT BIT(15)
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#define EP0_OUT_NULL BIT(14)
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#define EP0_OUT_FULL BIT(13)
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#define EP0_OUT_EMPTY BIT(12)
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#define EP0_IN_NAK_INT BIT(11)
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#define EP0_IN_DATA BIT(10)
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#define EP0_IN_FULL BIT(9)
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#define EP0_IN_EMPTY BIT(8)
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#define EP0_OUT_NULL_INT BIT(7)
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#define EP0_OUT_OR_INT BIT(6)
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#define EP0_OUT_INT BIT(5)
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#define EP0_IN_INT BIT(4)
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#define EP0_STALL_INT BIT(3)
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#define STG_END_INT BIT(2)
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#define STG_START_INT BIT(1)
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#define SETUP_INT BIT(0)
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#define EP0_STATUS_RW_BIT (BIT(16) | BIT(15) | BIT(11) | 0xFF)
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/*------- (0x0030) EP0 Interrupt Enable Register */
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#define EP0_PERR_NAK_EN BIT(16)
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#define EP0_OUT_NAK_EN BIT(15)
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#define EP0_IN_NAK_EN BIT(11)
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#define EP0_OUT_NULL_EN BIT(7)
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#define EP0_OUT_OR_EN BIT(6)
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#define EP0_OUT_EN BIT(5)
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#define EP0_IN_EN BIT(4)
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#define EP0_STALL_EN BIT(3)
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#define STG_END_EN BIT(2)
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#define STG_START_EN BIT(1)
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#define SETUP_EN BIT(0)
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#define EP0_INT_EN_BIT \
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(EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN)
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/*------- (0x0034) EP0 Length Register */
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#define EP0_LDATA 0x0000007F
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/*------- (0x0038) EP0 Read Register */
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/*------- (0x003C) EP0 Write Register */
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/*------- (0x0040:) EPN Control Register */
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#define EPN_EN BIT(31)
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#define EPN_BUF_TYPE BIT(30)
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#define EPN_BUF_SINGLE BIT(30)
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#define EPN_DIR0 BIT(26)
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#define EPN_MODE (BIT(25) | BIT(24))
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#define EPN_BULK 0
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#define EPN_INTERRUPT BIT(24)
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#define EPN_ISO BIT(25)
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#define EPN_OVERSEL BIT(17)
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#define EPN_AUTO BIT(16)
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#define EPN_IPIDCLR BIT(11)
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#define EPN_OPIDCLR BIT(10)
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#define EPN_BCLR BIT(9)
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#define EPN_CBCLR BIT(8)
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#define EPN_DEND BIT(7)
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#define EPN_DW (BIT(6) | BIT(5))
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#define EPN_DW4 0
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#define EPN_DW3 (BIT(6) | BIT(5))
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#define EPN_DW2 BIT(6)
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#define EPN_DW1 BIT(5)
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#define EPN_OSTL_EN BIT(4)
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#define EPN_ISTL BIT(3)
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#define EPN_OSTL BIT(2)
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#define EPN_ONAK BIT(0)
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/*------- (0x0044:) EPN Status Register */
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#define EPN_ISO_PIDERR BIT(29) /* R */
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#define EPN_OPID BIT(28) /* R */
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#define EPN_OUT_NOTKN BIT(27) /* R */
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#define EPN_ISO_OR BIT(26) /* R */
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#define EPN_ISO_CRC BIT(24) /* R */
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#define EPN_OUT_END_INT BIT(23) /* RW */
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#define EPN_OUT_OR_INT BIT(22) /* RW */
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#define EPN_OUT_NAK_ERR_INT BIT(21) /* RW */
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#define EPN_OUT_STALL_INT BIT(20) /* RW */
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#define EPN_OUT_INT BIT(19) /* RW */
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#define EPN_OUT_NULL_INT BIT(18) /* RW */
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#define EPN_OUT_FULL BIT(17) /* R */
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#define EPN_OUT_EMPTY BIT(16) /* R */
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#define EPN_IPID BIT(10) /* R */
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#define EPN_IN_NOTKN BIT(9) /* R */
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#define EPN_ISO_UR BIT(8) /* R */
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#define EPN_IN_END_INT BIT(7) /* RW */
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#define EPN_IN_NAK_ERR_INT BIT(5) /* RW */
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#define EPN_IN_STALL_INT BIT(4) /* RW */
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#define EPN_IN_INT BIT(3) /* RW */
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#define EPN_IN_DATA BIT(2) /* R */
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#define EPN_IN_FULL BIT(1) /* R */
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#define EPN_IN_EMPTY BIT(0) /* R */
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#define EPN_INT_EN \
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(EPN_OUT_END_INT | EPN_OUT_INT | EPN_IN_END_INT | EPN_IN_INT)
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/*------- (0x0048:) EPN Interrupt Enable Register */
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#define EPN_OUT_END_EN BIT(23) /* RW */
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#define EPN_OUT_OR_EN BIT(22) /* RW */
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#define EPN_OUT_NAK_ERR_EN BIT(21) /* RW */
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#define EPN_OUT_STALL_EN BIT(20) /* RW */
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#define EPN_OUT_EN BIT(19) /* RW */
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#define EPN_OUT_NULL_EN BIT(18) /* RW */
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#define EPN_IN_END_EN BIT(7) /* RW */
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#define EPN_IN_NAK_ERR_EN BIT(5) /* RW */
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#define EPN_IN_STALL_EN BIT(4) /* RW */
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#define EPN_IN_EN BIT(3) /* RW */
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/*------- (0x004C:) EPN Interrupt Enable Register */
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#define EPN_STOP_MODE BIT(11)
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#define EPN_DEND_SET BIT(10)
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#define EPN_BURST_SET BIT(9)
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#define EPN_STOP_SET BIT(8)
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#define EPN_DMA_EN BIT(4)
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#define EPN_DMAMODE0 BIT(0)
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/*------- (0x0050:) EPN MaxPacket & BaseAddress Register */
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#define EPN_BASEAD 0x1FFF0000
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#define EPN_MPKT 0x000007FF
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/*------- (0x0054:) EPN Length & DMA Count Register */
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#define EPN_DMACNT 0x01FF0000
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#define EPN_LDATA 0x000007FF
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/*------- (0x0058:) EPN Read Register */
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/*------- (0x005C:) EPN Write Register */
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/*------- (0x1000) AHBSCTR Register */
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#define WAIT_MODE BIT(0)
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/*------- (0x1004) AHBMCTR Register */
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#define ARBITER_CTR BIT(31) /* RW */
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#define MCYCLE_RST BIT(12) /* RW */
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#define ENDIAN_CTR (BIT(9) | BIT(8)) /* RW */
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#define ENDIAN_BYTE_SWAP BIT(9)
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#define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR
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#define HBUSREQ_MODE BIT(5) /* RW */
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#define HTRANS_MODE BIT(4) /* RW */
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#define WBURST_TYPE BIT(2) /* RW */
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#define BURST_TYPE (BIT(1) | BIT(0)) /* RW */
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#define BURST_MAX_16 0
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#define BURST_MAX_8 BIT(0)
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#define BURST_MAX_4 BIT(1)
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#define BURST_SINGLE BURST_TYPE
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/*------- (0x1008) AHBBINT Register */
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#define DMA_ENDINT 0xFFFE0000 /* RW */
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#define AHB_VBUS_INT BIT(13) /* RW */
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#define MBUS_ERRINT BIT(6) /* RW */
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#define SBUS_ERRINT0 BIT(4) /* RW */
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#define ERR_MASTER 0x0000000F /* R */
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/*------- (0x100C) AHBBINTEN Register */
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#define DMA_ENDINTEN 0xFFFE0000 /* RW */
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#define VBUS_INTEN BIT(13) /* RW */
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#define MBUS_ERRINTEN BIT(6) /* RW */
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#define SBUS_ERRINT0EN BIT(4) /* RW */
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/*------- (0x1010) EPCTR Register */
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#define DIRPD BIT(12) /* RW */
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#define VBUS_LEVEL BIT(8) /* R */
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#define PLL_RESUME BIT(5) /* RW */
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#define PLL_LOCK BIT(4) /* R */
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#define EPC_RST BIT(0) /* RW */
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/*------- (0x1014) USBF_EPTEST Register */
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#define LINESTATE (BIT(9) | BIT(8)) /* R */
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#define DM_LEVEL BIT(9) /* R */
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#define DP_LEVEL BIT(8) /* R */
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#define PHY_TST BIT(1) /* RW */
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#define PHY_TSTCLK BIT(0) /* RW */
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/*------- (0x1020) USBSSVER Register */
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#define AHBB_VER 0x00FF0000 /* R */
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#define EPC_VER 0x0000FF00 /* R */
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#define SS_VER 0x000000FF /* R */
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/*------- (0x1024) USBSSCONF Register */
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#define EP_AVAILABLE 0xFFFF0000 /* R */
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#define DMA_AVAILABLE 0x0000FFFF /* R */
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/*------- (0x1110:) EPNDCR1 Register */
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#define DCR1_EPN_DMACNT 0x00FF0000 /* RW */
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#define DCR1_EPN_DIR0 BIT(1) /* RW */
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#define DCR1_EPN_REQEN BIT(0) /* RW */
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/*------- (0x1114:) EPNDCR2 Register */
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#define DCR2_EPN_LMPKT 0x07FF0000 /* RW */
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#define DCR2_EPN_MPKT 0x000007FF /* RW */
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/*------- (0x1118:) EPNTADR Register */
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#define EPN_TADR 0xFFFFFFFF /* RW */
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/*===========================================================================*/
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/* Struct */
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/*------- ep_regs */
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struct ep_regs {
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u32 EP_CONTROL; /* EP Control */
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u32 EP_STATUS; /* EP Status */
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u32 EP_INT_ENA; /* EP Interrupt Enable */
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u32 EP_DMA_CTRL; /* EP DMA Control */
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u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */
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u32 EP_LEN_DCNT; /* EP Length & DMA count */
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u32 EP_READ; /* EP Read */
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u32 EP_WRITE; /* EP Write */
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};
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/*------- ep_dcr */
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struct ep_dcr {
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u32 EP_DCR1; /* EP_DCR1 */
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u32 EP_DCR2; /* EP_DCR2 */
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u32 EP_TADR; /* EP_TADR */
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u32 Reserved; /* Reserved */
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};
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/*------- Function Registers */
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struct fc_regs {
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u32 USB_CONTROL; /* (0x0000) USB Control */
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u32 USB_STATUS; /* (0x0004) USB Status */
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u32 USB_ADDRESS; /* (0x0008) USB Address */
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u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */
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u32 TEST_CONTROL; /* (0x0010) TEST Control */
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u32 reserved_14; /* (0x0014) Reserved */
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u32 SETUP_DATA0; /* (0x0018) Setup Data0 */
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u32 SETUP_DATA1; /* (0x001C) Setup Data1 */
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u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */
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u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */
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u32 EP0_CONTROL; /* (0x0028) EP0 Control */
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u32 EP0_STATUS; /* (0x002C) EP0 Status */
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u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */
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u32 EP0_LENGTH; /* (0x0034) EP0 Length */
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u32 EP0_READ; /* (0x0038) EP0 Read */
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u32 EP0_WRITE; /* (0x003C) EP0 Write */
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struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */
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u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */
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u32 AHBSCTR; /* (0x1000) AHBSCTR */
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u32 AHBMCTR; /* (0x1004) AHBMCTR */
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u32 AHBBINT; /* (0x1008) AHBBINT */
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u32 AHBBINTEN; /* (0x100C) AHBBINTEN */
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u32 EPCTR; /* (0x1010) EPCTR */
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u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */
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u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */
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u32 USBSSVER; /* (0x1020) USBSSVER */
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u32 USBSSCONF; /* (0x1024) USBSSCONF */
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u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */
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struct ep_dcr EP_DCR[REG_EP_NUM]; /* */
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u8 reserved_1200[0x1000 - 0x200]; /* Reserved */
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} __aligned(32);
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#define EP0_PACKETSIZE 64
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#define EP_PACKETSIZE 1024
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/* EPN RAM SIZE */
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#define D_RAM_SIZE_CTRL 64
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/* EPN Bulk Endpoint Max Packet Size */
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#define D_FS_RAM_SIZE_BULK 64
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#define D_HS_RAM_SIZE_BULK 512
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struct nbu2ss_udc;
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enum ep0_state {
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EP0_IDLE,
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EP0_IN_DATA_PHASE,
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EP0_OUT_DATA_PHASE,
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EP0_IN_STATUS_PHASE,
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EP0_OUT_STATUS_PAHSE,
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EP0_END_XFER,
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EP0_SUSPEND,
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EP0_STALL,
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};
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struct nbu2ss_req {
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struct usb_request req;
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struct list_head queue;
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u32 div_len;
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bool dma_flag;
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bool zero;
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bool unaligned;
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unsigned mapped:1;
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};
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struct nbu2ss_ep {
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struct usb_ep ep;
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struct list_head queue;
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struct nbu2ss_udc *udc;
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const struct usb_endpoint_descriptor *desc;
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u8 epnum;
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u8 direct;
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u8 ep_type;
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unsigned wedged:1;
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unsigned halted:1;
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unsigned stalled:1;
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u8 *virt_buf;
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dma_addr_t phys_buf;
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};
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struct nbu2ss_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct platform_device *pdev;
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struct device *dev;
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spinlock_t lock; /* Protects nbu2ss_udc structure fields */
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struct completion *pdone;
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enum ep0_state ep0state;
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enum usb_device_state devstate;
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struct usb_ctrlrequest ctrl;
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struct nbu2ss_req ep0_req;
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u8 ep0_buf[EP0_PACKETSIZE];
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struct nbu2ss_ep ep[NUM_ENDPOINTS];
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unsigned softconnect:1;
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unsigned vbus_active:1;
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unsigned linux_suspended:1;
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unsigned linux_resume:1;
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unsigned usb_suspended:1;
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unsigned remote_wakeup:1;
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unsigned udc_enabled:1;
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unsigned int mA;
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u32 curr_config; /* Current Configuration Number */
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struct fc_regs __iomem *p_regs;
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};
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/* USB register access structure */
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union usb_reg_access {
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struct {
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unsigned char DATA[4];
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} byte;
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unsigned int dw;
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};
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/*-------------------------------------------------------------------------*/
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#endif /* _LINUX_EMXX_H */
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