/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is part of wlcore
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*
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* Copyright (C) 2011 Texas Instruments Inc.
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*/
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#ifndef __WLCORE_H__
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#define __WLCORE_H__
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#include <linux/platform_device.h>
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#include "wlcore_i.h"
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#include "event.h"
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#include "boot.h"
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/* The maximum number of Tx descriptors in all chip families */
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#define WLCORE_MAX_TX_DESCRIPTORS 32
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/*
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* We always allocate this number of mac addresses. If we don't
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* have enough allocated addresses, the LAA bit is used
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*/
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#define WLCORE_NUM_MAC_ADDRESSES 3
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/* wl12xx/wl18xx maximum transmission power (in dBm) */
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#define WLCORE_MAX_TXPWR 25
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/* Texas Instruments pre assigned OUI */
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#define WLCORE_TI_OUI_ADDRESS 0x080028
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/* forward declaration */
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struct wl1271_tx_hw_descr;
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enum wl_rx_buf_align;
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struct wl1271_rx_descriptor;
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struct wlcore_ops {
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int (*setup)(struct wl1271 *wl);
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int (*identify_chip)(struct wl1271 *wl);
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int (*identify_fw)(struct wl1271 *wl);
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int (*boot)(struct wl1271 *wl);
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int (*plt_init)(struct wl1271 *wl);
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int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
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void *buf, size_t len);
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int (*ack_event)(struct wl1271 *wl);
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int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
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bool *timeout);
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int (*process_mailbox_events)(struct wl1271 *wl);
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u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
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void (*set_tx_desc_blocks)(struct wl1271 *wl,
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struct wl1271_tx_hw_descr *desc,
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u32 blks, u32 spare_blks);
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void (*set_tx_desc_data_len)(struct wl1271 *wl,
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struct wl1271_tx_hw_descr *desc,
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struct sk_buff *skb);
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enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
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u32 rx_desc);
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int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
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u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
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u32 data_len);
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int (*tx_delayed_compl)(struct wl1271 *wl);
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void (*tx_immediate_compl)(struct wl1271 *wl);
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int (*hw_init)(struct wl1271 *wl);
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int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
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void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status,
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struct wl_fw_status *fw_status);
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u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
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struct wl12xx_vif *wlvif);
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int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
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int (*get_mac)(struct wl1271 *wl);
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void (*set_tx_desc_csum)(struct wl1271 *wl,
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struct wl1271_tx_hw_descr *desc,
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struct sk_buff *skb);
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void (*set_rx_csum)(struct wl1271 *wl,
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struct wl1271_rx_descriptor *desc,
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struct sk_buff *skb);
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u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
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struct wl12xx_vif *wlvif);
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int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
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int (*handle_static_data)(struct wl1271 *wl,
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struct wl1271_static_data *static_data);
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int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
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struct cfg80211_scan_request *req);
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int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
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int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
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struct cfg80211_sched_scan_request *req,
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struct ieee80211_scan_ies *ies);
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void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
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int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
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int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key_conf);
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int (*channel_switch)(struct wl1271 *wl,
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struct wl12xx_vif *wlvif,
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struct ieee80211_channel_switch *ch_switch);
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u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
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void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
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int (*set_peer_cap)(struct wl1271 *wl,
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struct ieee80211_sta_ht_cap *ht_cap,
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bool allow_ht_operation,
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u32 rate_set, u8 hlid);
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u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr);
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bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid,
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struct wl1271_link *lnk);
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bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid,
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struct wl1271_link *lnk);
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int (*interrupt_notify)(struct wl1271 *wl, bool action);
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int (*rx_ba_filter)(struct wl1271 *wl, bool action);
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int (*ap_sleep)(struct wl1271 *wl);
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int (*smart_config_start)(struct wl1271 *wl, u32 group_bitmap);
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int (*smart_config_stop)(struct wl1271 *wl);
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int (*smart_config_set_group_key)(struct wl1271 *wl, u16 group_id,
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u8 key_len, u8 *key);
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int (*set_cac)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
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bool start);
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int (*dfs_master_restart)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
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};
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enum wlcore_partitions {
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PART_DOWN,
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PART_WORK,
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PART_BOOT,
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PART_DRPW,
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PART_TOP_PRCM_ELP_SOC,
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PART_PHY_INIT,
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PART_TABLE_LEN,
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};
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struct wlcore_partition {
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u32 size;
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u32 start;
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};
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struct wlcore_partition_set {
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struct wlcore_partition mem;
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struct wlcore_partition reg;
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struct wlcore_partition mem2;
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struct wlcore_partition mem3;
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};
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enum wlcore_registers {
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/* register addresses, used with partition translation */
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REG_ECPU_CONTROL,
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REG_INTERRUPT_NO_CLEAR,
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REG_INTERRUPT_ACK,
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REG_COMMAND_MAILBOX_PTR,
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REG_EVENT_MAILBOX_PTR,
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REG_INTERRUPT_TRIG,
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REG_INTERRUPT_MASK,
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REG_PC_ON_RECOVERY,
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REG_CHIP_ID_B,
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REG_CMD_MBOX_ADDRESS,
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/* data access memory addresses, used with partition translation */
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REG_SLV_MEM_DATA,
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REG_SLV_REG_DATA,
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/* raw data access memory addresses */
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REG_RAW_FW_STATUS_ADDR,
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REG_TABLE_LEN,
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};
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struct wl1271_stats {
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void *fw_stats;
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unsigned long fw_stats_update;
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size_t fw_stats_len;
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unsigned int retry_count;
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unsigned int excessive_retries;
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};
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struct wl1271 {
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bool initialized;
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struct ieee80211_hw *hw;
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bool mac80211_registered;
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struct device *dev;
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struct platform_device *pdev;
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void *if_priv;
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struct wl1271_if_operations *if_ops;
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int irq;
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int wakeirq;
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int irq_flags;
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int wakeirq_flags;
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spinlock_t wl_lock;
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enum wlcore_state state;
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enum wl12xx_fw_type fw_type;
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bool plt;
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enum plt_mode plt_mode;
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u8 fem_manuf;
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u8 last_vif_count;
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struct mutex mutex;
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unsigned long flags;
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struct wlcore_partition_set curr_part;
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struct wl1271_chip chip;
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int cmd_box_addr;
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u8 *fw;
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size_t fw_len;
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void *nvs;
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size_t nvs_len;
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s8 hw_pg_ver;
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/* address read from the fuse ROM */
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u32 fuse_oui_addr;
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u32 fuse_nic_addr;
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/* we have up to 2 MAC addresses */
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struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
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int channel;
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u8 system_hlid;
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unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)];
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unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
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unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
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unsigned long rate_policies_map[
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BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
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unsigned long klv_templates_map[
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BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
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u8 session_ids[WLCORE_MAX_LINKS];
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struct list_head wlvif_list;
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u8 sta_count;
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u8 ap_count;
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struct wl1271_acx_mem_map *target_mem_map;
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/* Accounting for allocated / available TX blocks on HW */
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u32 tx_blocks_freed;
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u32 tx_blocks_available;
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u32 tx_allocated_blocks;
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u32 tx_results_count;
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/* Accounting for allocated / available Tx packets in HW */
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u32 tx_pkts_freed[NUM_TX_QUEUES];
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u32 tx_allocated_pkts[NUM_TX_QUEUES];
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/* Transmitted TX packets counter for chipset interface */
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u32 tx_packets_count;
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/* Time-offset between host and chipset clocks */
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s64 time_offset;
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/* Frames scheduled for transmission, not handled yet */
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int tx_queue_count[NUM_TX_QUEUES];
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unsigned long queue_stop_reasons[
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NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES];
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/* Frames received, not handled yet by mac80211 */
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struct sk_buff_head deferred_rx_queue;
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/* Frames sent, not returned yet to mac80211 */
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struct sk_buff_head deferred_tx_queue;
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struct work_struct tx_work;
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struct workqueue_struct *freezable_wq;
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/* Pending TX frames */
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unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
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struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
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int tx_frames_cnt;
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/* FW Rx counter */
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u32 rx_counter;
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/* Intermediate buffer, used for packet aggregation */
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u8 *aggr_buf;
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u32 aggr_buf_size;
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/* Reusable dummy packet template */
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struct sk_buff *dummy_packet;
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/* Network stack work */
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struct work_struct netstack_work;
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/* FW log buffer */
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u8 *fwlog;
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/* Number of valid bytes in the FW log buffer */
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ssize_t fwlog_size;
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/* FW log end marker */
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u32 fwlog_end;
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/* FW memory block size */
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u32 fw_mem_block_size;
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/* Hardware recovery work */
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struct work_struct recovery_work;
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bool watchdog_recovery;
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/* Reg domain last configuration */
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DECLARE_BITMAP(reg_ch_conf_last, 64);
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/* Reg domain pending configuration */
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DECLARE_BITMAP(reg_ch_conf_pending, 64);
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/* Pointer that holds DMA-friendly block for the mailbox */
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void *mbox;
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/* The mbox event mask */
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u32 event_mask;
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/* events to unmask only when ap interface is up */
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u32 ap_event_mask;
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/* Mailbox pointers */
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u32 mbox_size;
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u32 mbox_ptr[2];
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/* Are we currently scanning */
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struct wl12xx_vif *scan_wlvif;
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struct wl1271_scan scan;
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struct delayed_work scan_complete_work;
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struct ieee80211_vif *roc_vif;
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struct delayed_work roc_complete_work;
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struct wl12xx_vif *sched_vif;
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/* The current band */
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enum nl80211_band band;
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struct completion *elp_compl;
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/* in dBm */
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int power_level;
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struct wl1271_stats stats;
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__le32 *buffer_32;
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u32 buffer_cmd;
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u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
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void *raw_fw_status;
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struct wl_fw_status *fw_status;
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struct wl1271_tx_hw_res_if *tx_res_if;
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/* Current chipset configuration */
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struct wlcore_conf conf;
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bool sg_enabled;
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bool enable_11a;
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int recovery_count;
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/* Most recently reported noise in dBm */
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s8 noise;
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/* bands supported by this instance of wl12xx */
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struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
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/*
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* wowlan trigger was configured during suspend.
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* (currently, only "ANY" trigger is supported)
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*/
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bool wow_enabled;
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bool irq_wake_enabled;
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/*
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* AP-mode - links indexed by HLID. The global and broadcast links
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* are always active.
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*/
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struct wl1271_link links[WLCORE_MAX_LINKS];
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/* number of currently active links */
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int active_link_count;
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/* Fast/slow links bitmap according to FW */
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unsigned long fw_fast_lnk_map;
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/* AP-mode - a bitmap of links currently in PS mode according to FW */
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unsigned long ap_fw_ps_map;
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/* AP-mode - a bitmap of links currently in PS mode in mac80211 */
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unsigned long ap_ps_map;
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/* Quirks of specific hardware revisions */
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unsigned int quirks;
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/* number of currently active RX BA sessions */
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int ba_rx_session_count;
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/* Maximum number of supported RX BA sessions */
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int ba_rx_session_count_max;
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/* AP-mode - number of currently connected stations */
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int active_sta_count;
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/* Flag determining whether AP should broadcast OFDM-only rates */
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bool ofdm_only_ap;
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/* last wlvif we transmitted from */
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struct wl12xx_vif *last_wlvif;
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/* work to fire when Tx is stuck */
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struct delayed_work tx_watchdog_work;
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struct wlcore_ops *ops;
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/* pointer to the lower driver partition table */
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const struct wlcore_partition_set *ptable;
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/* pointer to the lower driver register table */
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const int *rtable;
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/* name of the firmwares to load - for PLT, single role, multi-role */
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const char *plt_fw_name;
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const char *sr_fw_name;
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const char *mr_fw_name;
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u8 scan_templ_id_2_4;
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u8 scan_templ_id_5;
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u8 sched_scan_templ_id_2_4;
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u8 sched_scan_templ_id_5;
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u8 max_channels_5;
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/* per-chip-family private structure */
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void *priv;
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/* number of TX descriptors the HW supports. */
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u32 num_tx_desc;
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/* number of RX descriptors the HW supports. */
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u32 num_rx_desc;
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/* number of links the HW supports */
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u8 num_links;
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/* max stations a single AP can support */
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u8 max_ap_stations;
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/* translate HW Tx rates to standard rate-indices */
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const u8 **band_rate_to_idx;
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/* size of table for HW rates that can be received from chip */
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u8 hw_tx_rate_tbl_size;
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/* this HW rate and below are considered HT rates for this chip */
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u8 hw_min_ht_rate;
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/* HW HT (11n) capabilities */
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struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
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/* the current dfs region */
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enum nl80211_dfs_regions dfs_region;
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bool radar_debug_mode;
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/* size of the private FW status data */
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size_t fw_status_len;
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size_t fw_status_priv_len;
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/* RX Data filter rule state - enabled/disabled */
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unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)];
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/* size of the private static data */
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size_t static_data_priv_len;
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/* the current channel type */
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enum nl80211_channel_type channel_type;
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/* mutex for protecting the tx_flush function */
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struct mutex flush_mutex;
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/* sleep auth value currently configured to FW */
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int sleep_auth;
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/* the number of allocated MAC addresses in this chip */
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int num_mac_addr;
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/* minimum FW version required for the driver to work in single-role */
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unsigned int min_sr_fw_ver[NUM_FW_VER];
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/* minimum FW version required for the driver to work in multi-role */
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unsigned int min_mr_fw_ver[NUM_FW_VER];
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struct completion nvs_loading_complete;
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/* interface combinations supported by the hw */
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const struct ieee80211_iface_combination *iface_combinations;
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u8 n_iface_combinations;
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/* dynamic fw traces */
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u32 dynamic_fw_traces;
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/* time sync zone master */
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u8 zone_master_mac_addr[ETH_ALEN];
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};
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int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
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int wlcore_remove(struct platform_device *pdev);
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struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
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u32 mbox_size);
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int wlcore_free_hw(struct wl1271 *wl);
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int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key_conf);
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void wlcore_regdomain_config(struct wl1271 *wl);
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void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif,
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struct wl1271_station *wl_sta, bool in_conn);
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static inline void
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wlcore_set_ht_cap(struct wl1271 *wl, enum nl80211_band band,
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struct ieee80211_sta_ht_cap *ht_cap)
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{
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memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
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}
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/* Tell wlcore not to care about this element when checking the version */
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#define WLCORE_FW_VER_IGNORE -1
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static inline void
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wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
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unsigned int iftype_sr, unsigned int major_sr,
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unsigned int subtype_sr, unsigned int minor_sr,
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unsigned int iftype_mr, unsigned int major_mr,
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unsigned int subtype_mr, unsigned int minor_mr)
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{
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wl->min_sr_fw_ver[FW_VER_CHIP] = chip;
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wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr;
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wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr;
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wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr;
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wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr;
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wl->min_mr_fw_ver[FW_VER_CHIP] = chip;
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wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr;
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wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr;
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wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr;
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wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr;
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}
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/* Firmware image load chunk size */
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#define CHUNK_SIZE 16384
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/* Quirks */
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/* Each RX/TX transaction requires an end-of-transaction transfer */
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#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
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/* wl127x and SPI don't support SDIO block size alignment */
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#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
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/* means aggregated Rx packets are aligned to a SDIO block */
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#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
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/* Older firmwares did not implement the FW logger over bus feature */
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#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
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/* Older firmwares use an old NVS format */
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#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
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/* pad only the last frame in the aggregate buffer */
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#define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
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/* extra header space is required for TKIP */
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#define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
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/* Some firmwares not support sched scans while connected */
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#define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
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/* separate probe response templates for one-shot and sched scans */
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#define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
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/* Firmware requires reg domain configuration for active calibration */
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#define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
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/* The FW only support a zero session id for AP */
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#define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12)
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/* TODO: move all these common registers and values elsewhere */
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#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
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/* ELP register commands */
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#define ELPCTRL_WAKE_UP 0x1
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#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
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#define ELPCTRL_SLEEP 0x0
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/* ELP WLAN_READY bit */
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#define ELPCTRL_WLAN_READY 0x2
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/*************************************************************************
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Interrupt Trigger Register (Host -> WiLink)
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**************************************************************************/
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/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
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/*
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* The host sets this bit to inform the Wlan
|
* FW that a TX packet is in the XFER
|
* Buffer #0.
|
*/
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#define INTR_TRIG_TX_PROC0 BIT(2)
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/*
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* The host sets this bit to inform the FW
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* that it read a packet from RX XFER
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* Buffer #0.
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*/
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#define INTR_TRIG_RX_PROC0 BIT(3)
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#define INTR_TRIG_DEBUG_ACK BIT(4)
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|
#define INTR_TRIG_STATE_CHANGED BIT(5)
|
|
/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
|
|
/*
|
* The host sets this bit to inform the FW
|
* that it read a packet from RX XFER
|
* Buffer #1.
|
*/
|
#define INTR_TRIG_RX_PROC1 BIT(17)
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|
/*
|
* The host sets this bit to inform the Wlan
|
* hardware that a TX packet is in the XFER
|
* Buffer #1.
|
*/
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#define INTR_TRIG_TX_PROC1 BIT(18)
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#define ACX_SLV_SOFT_RESET_BIT BIT(1)
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#define SOFT_RESET_MAX_TIME 1000000
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#define SOFT_RESET_STALL_TIME 1000
|
|
#define ECPU_CONTROL_HALT 0x00000101
|
|
#define WELP_ARM_COMMAND_VAL 0x4
|
|
#endif /* __WLCORE_H__ */
|
