// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Firmware I/O code for mac80211 ST-Ericsson CW1200 drivers
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*
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* Copyright (c) 2010, ST-Ericsson
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* Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
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*
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* Based on:
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* ST-Ericsson UMAC CW1200 driver which is
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* Copyright (c) 2010, ST-Ericsson
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* Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
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*/
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#include <linux/vmalloc.h>
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#include <linux/sched.h>
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#include <linux/firmware.h>
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#include "cw1200.h"
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#include "fwio.h"
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#include "hwio.h"
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#include "hwbus.h"
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#include "bh.h"
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static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
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{
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int hw_type = -1;
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u32 silicon_type = (config_reg_val >> 24) & 0x7;
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u32 silicon_vers = (config_reg_val >> 31) & 0x1;
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switch (silicon_type) {
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case 0x00:
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*major_revision = 1;
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hw_type = HIF_9000_SILICON_VERSATILE;
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break;
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case 0x01:
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case 0x02: /* CW1x00 */
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case 0x04: /* CW1x60 */
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*major_revision = silicon_type;
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if (silicon_vers)
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hw_type = HIF_8601_VERSATILE;
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else
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hw_type = HIF_8601_SILICON;
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break;
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default:
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break;
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}
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return hw_type;
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}
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static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
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{
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int ret, block, num_blocks;
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unsigned i;
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u32 val32;
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u32 put = 0, get = 0;
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u8 *buf = NULL;
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const char *fw_path;
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const struct firmware *firmware = NULL;
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/* Macroses are local. */
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#define APB_WRITE(reg, val) \
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do { \
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ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
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if (ret < 0) \
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goto exit; \
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} while (0)
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#define APB_WRITE2(reg, val) \
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do { \
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ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
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if (ret < 0) \
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goto free_buffer; \
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} while (0)
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#define APB_READ(reg, val) \
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do { \
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ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
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if (ret < 0) \
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goto free_buffer; \
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} while (0)
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#define REG_WRITE(reg, val) \
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do { \
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ret = cw1200_reg_write_32(priv, (reg), (val)); \
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if (ret < 0) \
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goto exit; \
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} while (0)
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#define REG_READ(reg, val) \
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do { \
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ret = cw1200_reg_read_32(priv, (reg), &(val)); \
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if (ret < 0) \
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goto exit; \
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} while (0)
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switch (priv->hw_revision) {
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case CW1200_HW_REV_CUT10:
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fw_path = FIRMWARE_CUT10;
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if (!priv->sdd_path)
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priv->sdd_path = SDD_FILE_10;
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break;
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case CW1200_HW_REV_CUT11:
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fw_path = FIRMWARE_CUT11;
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if (!priv->sdd_path)
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priv->sdd_path = SDD_FILE_11;
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break;
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case CW1200_HW_REV_CUT20:
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fw_path = FIRMWARE_CUT20;
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if (!priv->sdd_path)
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priv->sdd_path = SDD_FILE_20;
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break;
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case CW1200_HW_REV_CUT22:
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fw_path = FIRMWARE_CUT22;
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if (!priv->sdd_path)
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priv->sdd_path = SDD_FILE_22;
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break;
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case CW1X60_HW_REV:
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fw_path = FIRMWARE_CW1X60;
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if (!priv->sdd_path)
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priv->sdd_path = SDD_FILE_CW1X60;
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break;
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default:
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pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
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return -EINVAL;
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}
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/* Initialize common registers */
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APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
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APB_WRITE(DOWNLOAD_PUT_REG, 0);
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APB_WRITE(DOWNLOAD_GET_REG, 0);
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APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
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APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
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/* Write the NOP Instruction */
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REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
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REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
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/* Release CPU from RESET */
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REG_READ(ST90TDS_CONFIG_REG_ID, val32);
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val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
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REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
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/* Enable Clock */
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val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
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REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
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/* Load a firmware file */
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ret = request_firmware(&firmware, fw_path, priv->pdev);
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if (ret) {
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pr_err("Can't load firmware file %s.\n", fw_path);
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goto exit;
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}
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buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
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if (!buf) {
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pr_err("Can't allocate firmware load buffer.\n");
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ret = -ENOMEM;
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goto firmware_release;
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}
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/* Check if the bootloader is ready */
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for (i = 0; i < 100; i += 1 + i / 2) {
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APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
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if (val32 == DOWNLOAD_I_AM_HERE)
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break;
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mdelay(i);
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} /* End of for loop */
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if (val32 != DOWNLOAD_I_AM_HERE) {
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pr_err("Bootloader is not ready.\n");
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ret = -ETIMEDOUT;
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goto free_buffer;
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}
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/* Calculcate number of download blocks */
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num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
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/* Updating the length in Download Ctrl Area */
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val32 = firmware->size; /* Explicit cast from size_t to u32 */
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APB_WRITE2(DOWNLOAD_IMAGE_SIZE_REG, val32);
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/* Firmware downloading loop */
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for (block = 0; block < num_blocks; block++) {
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size_t tx_size;
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size_t block_size;
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/* check the download status */
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APB_READ(DOWNLOAD_STATUS_REG, val32);
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if (val32 != DOWNLOAD_PENDING) {
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pr_err("Bootloader reported error %d.\n", val32);
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ret = -EIO;
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goto free_buffer;
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}
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/* loop until put - get <= 24K */
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for (i = 0; i < 100; i++) {
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APB_READ(DOWNLOAD_GET_REG, get);
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if ((put - get) <=
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(DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
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break;
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mdelay(i);
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}
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if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
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pr_err("Timeout waiting for FIFO.\n");
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ret = -ETIMEDOUT;
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goto free_buffer;
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}
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/* calculate the block size */
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tx_size = block_size = min_t(size_t, firmware->size - put,
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DOWNLOAD_BLOCK_SIZE);
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memcpy(buf, &firmware->data[put], block_size);
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if (block_size < DOWNLOAD_BLOCK_SIZE) {
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memset(&buf[block_size], 0,
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DOWNLOAD_BLOCK_SIZE - block_size);
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tx_size = DOWNLOAD_BLOCK_SIZE;
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}
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/* send the block to sram */
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ret = cw1200_apb_write(priv,
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CW1200_APB(DOWNLOAD_FIFO_OFFSET +
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(put & (DOWNLOAD_FIFO_SIZE - 1))),
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buf, tx_size);
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if (ret < 0) {
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pr_err("Can't write firmware block @ %d!\n",
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put & (DOWNLOAD_FIFO_SIZE - 1));
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goto free_buffer;
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}
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/* update the put register */
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put += block_size;
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APB_WRITE2(DOWNLOAD_PUT_REG, put);
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} /* End of firmware download loop */
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/* Wait for the download completion */
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for (i = 0; i < 300; i += 1 + i / 2) {
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APB_READ(DOWNLOAD_STATUS_REG, val32);
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if (val32 != DOWNLOAD_PENDING)
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break;
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mdelay(i);
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}
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if (val32 != DOWNLOAD_SUCCESS) {
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pr_err("Wait for download completion failed: 0x%.8X\n", val32);
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ret = -ETIMEDOUT;
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goto free_buffer;
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} else {
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pr_info("Firmware download completed.\n");
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ret = 0;
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}
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free_buffer:
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kfree(buf);
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firmware_release:
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release_firmware(firmware);
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exit:
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return ret;
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#undef APB_WRITE
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#undef APB_WRITE2
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#undef APB_READ
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#undef REG_WRITE
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#undef REG_READ
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}
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static int config_reg_read(struct cw1200_common *priv, u32 *val)
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{
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switch (priv->hw_type) {
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case HIF_9000_SILICON_VERSATILE: {
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u16 val16;
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int ret = cw1200_reg_read_16(priv,
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ST90TDS_CONFIG_REG_ID,
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&val16);
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if (ret < 0)
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return ret;
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*val = val16;
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return 0;
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}
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case HIF_8601_VERSATILE:
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case HIF_8601_SILICON:
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default:
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cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
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break;
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}
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return 0;
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}
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static int config_reg_write(struct cw1200_common *priv, u32 val)
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{
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switch (priv->hw_type) {
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case HIF_9000_SILICON_VERSATILE:
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return cw1200_reg_write_16(priv,
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ST90TDS_CONFIG_REG_ID,
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(u16)val);
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case HIF_8601_VERSATILE:
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case HIF_8601_SILICON:
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default:
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return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
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}
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return 0;
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}
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int cw1200_load_firmware(struct cw1200_common *priv)
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{
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int ret;
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int i;
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u32 val32;
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u16 val16;
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int major_revision = -1;
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/* Read CONFIG Register */
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ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
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if (ret < 0) {
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pr_err("Can't read config register.\n");
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goto out;
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}
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if (val32 == 0 || val32 == 0xffffffff) {
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pr_err("Bad config register value (0x%08x)\n", val32);
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ret = -EIO;
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goto out;
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}
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ret = cw1200_get_hw_type(val32, &major_revision);
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if (ret < 0) {
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pr_err("Can't deduce hardware type.\n");
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goto out;
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}
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priv->hw_type = ret;
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/* Set DPLL Reg value, and read back to confirm writes work */
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ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
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cw1200_dpll_from_clk(priv->hw_refclk));
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if (ret < 0) {
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pr_err("Can't write DPLL register.\n");
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goto out;
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}
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msleep(20);
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ret = cw1200_reg_read_32(priv,
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ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
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if (ret < 0) {
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pr_err("Can't read DPLL register.\n");
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goto out;
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}
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if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
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pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
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cw1200_dpll_from_clk(priv->hw_refclk), val32);
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ret = -EIO;
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goto out;
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}
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/* Set wakeup bit in device */
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ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
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if (ret < 0) {
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pr_err("set_wakeup: can't read control register.\n");
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goto out;
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}
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ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
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val16 | ST90TDS_CONT_WUP_BIT);
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if (ret < 0) {
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pr_err("set_wakeup: can't write control register.\n");
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goto out;
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}
|
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/* Wait for wakeup */
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for (i = 0; i < 300; i += (1 + i / 2)) {
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ret = cw1200_reg_read_16(priv,
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ST90TDS_CONTROL_REG_ID, &val16);
|
if (ret < 0) {
|
pr_err("wait_for_wakeup: can't read control register.\n");
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goto out;
|
}
|
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if (val16 & ST90TDS_CONT_RDY_BIT)
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break;
|
|
msleep(i);
|
}
|
|
if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
|
pr_err("wait_for_wakeup: device is not responding.\n");
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ret = -ETIMEDOUT;
|
goto out;
|
}
|
|
switch (major_revision) {
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case 1:
|
/* CW1200 Hardware detection logic : Check for CUT1.1 */
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ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
|
if (ret) {
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pr_err("HW detection: can't read CUT ID.\n");
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goto out;
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}
|
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switch (val32) {
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case CW1200_CUT_11_ID_STR:
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pr_info("CW1x00 Cut 1.1 silicon detected.\n");
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priv->hw_revision = CW1200_HW_REV_CUT11;
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break;
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default:
|
pr_info("CW1x00 Cut 1.0 silicon detected.\n");
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priv->hw_revision = CW1200_HW_REV_CUT10;
|
break;
|
}
|
|
/* According to ST-E, CUT<2.0 has busted BA TID0-3.
|
Just disable it entirely...
|
*/
|
priv->ba_rx_tid_mask = 0;
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priv->ba_tx_tid_mask = 0;
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break;
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case 2: {
|
u32 ar1, ar2, ar3;
|
ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
|
if (ret) {
|
pr_err("(1) HW detection: can't read CUT ID\n");
|
goto out;
|
}
|
ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
|
if (ret) {
|
pr_err("(2) HW detection: can't read CUT ID.\n");
|
goto out;
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}
|
|
ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
|
if (ret) {
|
pr_err("(3) HW detection: can't read CUT ID.\n");
|
goto out;
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}
|
|
if (ar1 == CW1200_CUT_22_ID_STR1 &&
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ar2 == CW1200_CUT_22_ID_STR2 &&
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ar3 == CW1200_CUT_22_ID_STR3) {
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pr_info("CW1x00 Cut 2.2 silicon detected.\n");
|
priv->hw_revision = CW1200_HW_REV_CUT22;
|
} else {
|
pr_info("CW1x00 Cut 2.0 silicon detected.\n");
|
priv->hw_revision = CW1200_HW_REV_CUT20;
|
}
|
break;
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}
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case 4:
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pr_info("CW1x60 silicon detected.\n");
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priv->hw_revision = CW1X60_HW_REV;
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break;
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default:
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pr_err("Unsupported silicon major revision %d.\n",
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major_revision);
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ret = -ENOTSUPP;
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goto out;
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}
|
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/* Checking for access mode */
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ret = config_reg_read(priv, &val32);
|
if (ret < 0) {
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pr_err("Can't read config register.\n");
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goto out;
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}
|
|
if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
|
pr_err("Device is already in QUEUE mode!\n");
|
ret = -EINVAL;
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goto out;
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}
|
|
switch (priv->hw_type) {
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case HIF_8601_SILICON:
|
if (priv->hw_revision == CW1X60_HW_REV) {
|
pr_err("Can't handle CW1160/1260 firmware load yet.\n");
|
ret = -ENOTSUPP;
|
goto out;
|
}
|
ret = cw1200_load_firmware_cw1200(priv);
|
break;
|
default:
|
pr_err("Can't perform firmware load for hw type %d.\n",
|
priv->hw_type);
|
ret = -ENOTSUPP;
|
goto out;
|
}
|
if (ret < 0) {
|
pr_err("Firmware load error.\n");
|
goto out;
|
}
|
|
/* Enable interrupt signalling */
|
priv->hwbus_ops->lock(priv->hwbus_priv);
|
ret = __cw1200_irq_enable(priv, 1);
|
priv->hwbus_ops->unlock(priv->hwbus_priv);
|
if (ret < 0)
|
goto unsubscribe;
|
|
/* Configure device for MESSSAGE MODE */
|
ret = config_reg_read(priv, &val32);
|
if (ret < 0) {
|
pr_err("Can't read config register.\n");
|
goto unsubscribe;
|
}
|
ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
|
if (ret < 0) {
|
pr_err("Can't write config register.\n");
|
goto unsubscribe;
|
}
|
|
/* Unless we read the CONFIG Register we are
|
* not able to get an interrupt
|
*/
|
mdelay(10);
|
config_reg_read(priv, &val32);
|
|
out:
|
return ret;
|
|
unsubscribe:
|
/* Disable interrupt signalling */
|
priv->hwbus_ops->lock(priv->hwbus_priv);
|
ret = __cw1200_irq_enable(priv, 0);
|
priv->hwbus_ops->unlock(priv->hwbus_priv);
|
return ret;
|
}
|
