/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#ifndef __RTL92C_DEF_H__
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#define __RTL92C_DEF_H__
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#define PHY_RSSI_SLID_WIN_MAX 100
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#define PHY_LINKQUALITY_SLID_WIN_MAX 20
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#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
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#define RX_SMOOTH_FACTOR 20
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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#define RX_MPDU_QUEUE 0
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#define RX_CMD_QUEUE 1
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#define CHIP_VER_B BIT(4)
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define RF_TYPE_1T2R BIT(1)
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#define CHIP_92C_BITMASK BIT(0)
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#define CHIP_UNKNOWN BIT(7)
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#define CHIP_92C_1T2R 0x03
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#define CHIP_92C 0x01
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#define CHIP_88C 0x00
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enum version_8192c {
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VERSION_A_CHIP_92C = 0x01,
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VERSION_A_CHIP_88C = 0x00,
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VERSION_B_CHIP_92C = 0x11,
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VERSION_B_CHIP_88C = 0x10,
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VERSION_TEST_CHIP_88C = 0x00,
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VERSION_TEST_CHIP_92C = 0x01,
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VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
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VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
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VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
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VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
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VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
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VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
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VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
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VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
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VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
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VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
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VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
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VERSION_UNKNOWN = 0x88,
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};
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enum rtl819x_loopback_e {
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RTL819X_NO_LOOPBACK = 0,
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RTL819X_MAC_LOOPBACK = 1,
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RTL819X_DMA_LOOPBACK = 2,
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RTL819X_CCK_LOOPBACK = 3,
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};
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enum rf_optype {
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RF_OP_BY_SW_3WIRE = 0,
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RF_OP_BY_FW,
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RF_OP_MAX
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};
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enum rf_power_state {
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RF_ON,
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RF_OFF,
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RF_SLEEP,
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RF_SHUT_DOWN,
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};
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enum power_save_mode {
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POWER_SAVE_MODE_ACTIVE,
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POWER_SAVE_MODE_SAVE,
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};
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enum power_polocy_config {
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POWERCFG_MAX_POWER_SAVINGS,
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POWERCFG_GLOBAL_POWER_SAVINGS,
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POWERCFG_LOCAL_POWER_SAVINGS,
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POWERCFG_LENOVO,
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};
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enum interface_select_pci {
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INTF_SEL1_MINICARD = 0,
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INTF_SEL0_PCIE = 1,
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INTF_SEL2_RSV = 2,
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INTF_SEL3_RSV = 3,
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};
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enum rtl_desc_qsel {
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QSLT_BK = 0x2,
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QSLT_BE = 0x0,
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QSLT_VI = 0x5,
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QSLT_VO = 0x7,
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QSLT_BEACON = 0x10,
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QSLT_HIGH = 0x11,
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QSLT_MGNT = 0x12,
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QSLT_CMD = 0x13,
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};
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struct phy_sts_cck_8192s_t {
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u8 adc_pwdb_X[4];
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u8 sq_rpt;
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u8 cck_agc_rpt;
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};
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struct h2c_cmd_8192c {
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u8 element_id;
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u32 cmd_len;
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u8 *p_cmdbuffer;
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};
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#endif
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