/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BRCM_DMA_H_
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#define _BRCM_DMA_H_
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#include <linux/delay.h>
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#include <linux/skbuff.h>
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#include "types.h" /* forward structure declarations */
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/* map/unmap direction */
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#define DMA_TX 1 /* TX direction for DMA */
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#define DMA_RX 2 /* RX direction for DMA */
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/* DMA structure:
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* support two DMA engines: 32 bits address or 64 bit addressing
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* basic DMA register set is per channel(transmit or receive)
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* a pair of channels is defined for convenience
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*/
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/* 32 bits addressing */
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struct dma32diag { /* diag access */
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u32 fifoaddr; /* diag address */
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u32 fifodatalow; /* low 32bits of data */
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u32 fifodatahigh; /* high 32bits of data */
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u32 pad; /* reserved */
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};
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/* 64 bits addressing */
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/* dma registers per channel(xmt or rcv) */
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struct dma64regs {
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u32 control; /* enable, et al */
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u32 ptr; /* last descriptor posted to chip */
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u32 addrlow; /* desc ring base address low 32-bits (8K aligned) */
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u32 addrhigh; /* desc ring base address bits 63:32 (8K aligned) */
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u32 status0; /* current descriptor, xmt state */
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u32 status1; /* active descriptor, xmt error */
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};
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/* range param for dma_getnexttxp() and dma_txreclaim */
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enum txd_range {
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DMA_RANGE_ALL = 1,
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DMA_RANGE_TRANSMITTED,
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DMA_RANGE_TRANSFERED
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};
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/*
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* Exported data structure (read-only)
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*/
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/* export structure */
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struct dma_pub {
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uint txavail; /* # free tx descriptors */
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uint dmactrlflags; /* dma control flags */
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/* rx error counters */
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uint rxgiants; /* rx giant frames */
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uint rxnobuf; /* rx out of dma descriptors */
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/* tx error counters */
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uint txnobuf; /* tx out of dma descriptors */
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};
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extern struct dma_pub *dma_attach(char *name, struct brcms_c_info *wlc,
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uint txregbase, uint rxregbase,
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uint ntxd, uint nrxd,
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uint rxbufsize, int rxextheadroom,
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uint nrxpost, uint rxoffset);
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void dma_rxinit(struct dma_pub *pub);
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int dma_rx(struct dma_pub *pub, struct sk_buff_head *skb_list);
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bool dma_rxfill(struct dma_pub *pub);
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bool dma_rxreset(struct dma_pub *pub);
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bool dma_txreset(struct dma_pub *pub);
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void dma_txinit(struct dma_pub *pub);
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int dma_txfast(struct brcms_c_info *wlc, struct dma_pub *pub,
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struct sk_buff *p0);
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void dma_txflush(struct dma_pub *pub);
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int dma_txpending(struct dma_pub *pub);
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void dma_kick_tx(struct dma_pub *pub);
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void dma_txsuspend(struct dma_pub *pub);
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bool dma_txsuspended(struct dma_pub *pub);
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void dma_txresume(struct dma_pub *pub);
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void dma_txreclaim(struct dma_pub *pub, enum txd_range range);
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void dma_rxreclaim(struct dma_pub *pub);
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void dma_detach(struct dma_pub *pub);
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unsigned long dma_getvar(struct dma_pub *pub, const char *name);
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struct sk_buff *dma_getnexttxp(struct dma_pub *pub, enum txd_range range);
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void dma_counterreset(struct dma_pub *pub);
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void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
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(void *pkt, void *arg_a), void *arg_a);
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/*
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* DMA(Bug) on bcm47xx chips seems to declare that the packet is ready, but
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* the packet length is not updated yet (by DMA) on the expected time.
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* Workaround is to hold processor till DMA updates the length, and stay off
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* the bus to allow DMA update the length in buffer
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*/
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static inline void dma_spin_for_len(uint len, struct sk_buff *head)
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{
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#if defined(CONFIG_BCM47XX)
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if (!len) {
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while (!(len = *(u16 *) KSEG1ADDR(head->data)))
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udelay(1);
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*(u16 *) (head->data) = cpu_to_le16((u16) len);
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}
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#endif /* defined(CONFIG_BCM47XX) */
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}
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#endif /* _BRCM_DMA_H_ */
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