/*
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* Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mlx5/driver.h>
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#include "mlx5_core.h"
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/* Scheduling element fw management */
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int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
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void *ctx, u32 *element_id)
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{
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u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {};
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u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {};
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void *schedc;
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int err;
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schedc = MLX5_ADDR_OF(create_scheduling_element_in, in,
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scheduling_context);
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MLX5_SET(create_scheduling_element_in, in, opcode,
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MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT);
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MLX5_SET(create_scheduling_element_in, in, scheduling_hierarchy,
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hierarchy);
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memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
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err = mlx5_cmd_exec_inout(dev, create_scheduling_element, in, out);
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if (err)
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return err;
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*element_id = MLX5_GET(create_scheduling_element_out, out,
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scheduling_element_id);
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return 0;
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}
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int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
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void *ctx, u32 element_id,
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u32 modify_bitmask)
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{
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u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {};
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void *schedc;
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schedc = MLX5_ADDR_OF(modify_scheduling_element_in, in,
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scheduling_context);
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MLX5_SET(modify_scheduling_element_in, in, opcode,
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MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT);
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MLX5_SET(modify_scheduling_element_in, in, scheduling_element_id,
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element_id);
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MLX5_SET(modify_scheduling_element_in, in, modify_bitmask,
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modify_bitmask);
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MLX5_SET(modify_scheduling_element_in, in, scheduling_hierarchy,
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hierarchy);
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memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
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return mlx5_cmd_exec_in(dev, modify_scheduling_element, in);
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}
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int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
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u32 element_id)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {};
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MLX5_SET(destroy_scheduling_element_in, in, opcode,
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MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
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MLX5_SET(destroy_scheduling_element_in, in, scheduling_element_id,
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element_id);
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MLX5_SET(destroy_scheduling_element_in, in, scheduling_hierarchy,
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hierarchy);
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return mlx5_cmd_exec_in(dev, destroy_scheduling_element, in);
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}
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static bool mlx5_rl_are_equal_raw(struct mlx5_rl_entry *entry, void *rl_in,
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u16 uid)
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{
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return (!memcmp(entry->rl_raw, rl_in, sizeof(entry->rl_raw)) &&
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entry->uid == uid);
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}
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/* Finds an entry where we can register the given rate
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* If the rate already exists, return the entry where it is registered,
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* otherwise return the first available entry.
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* If the table is full, return NULL
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*/
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static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
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void *rl_in, u16 uid, bool dedicated)
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{
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struct mlx5_rl_entry *ret_entry = NULL;
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bool empty_found = false;
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int i;
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for (i = 0; i < table->max_size; i++) {
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if (dedicated) {
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if (!table->rl_entry[i].refcount)
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return &table->rl_entry[i];
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continue;
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}
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if (table->rl_entry[i].refcount) {
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if (table->rl_entry[i].dedicated)
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continue;
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if (mlx5_rl_are_equal_raw(&table->rl_entry[i], rl_in,
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uid))
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return &table->rl_entry[i];
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} else if (!empty_found) {
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empty_found = true;
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ret_entry = &table->rl_entry[i];
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}
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}
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return ret_entry;
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}
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static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
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struct mlx5_rl_entry *entry, bool set)
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{
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u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {};
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void *pp_context;
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pp_context = MLX5_ADDR_OF(set_pp_rate_limit_in, in, ctx);
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MLX5_SET(set_pp_rate_limit_in, in, opcode,
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MLX5_CMD_OP_SET_PP_RATE_LIMIT);
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MLX5_SET(set_pp_rate_limit_in, in, uid, entry->uid);
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MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, entry->index);
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if (set)
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memcpy(pp_context, entry->rl_raw, sizeof(entry->rl_raw));
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return mlx5_cmd_exec_in(dev, set_pp_rate_limit, in);
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}
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bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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return (rate <= table->max_rate && rate >= table->min_rate);
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}
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EXPORT_SYMBOL(mlx5_rl_is_in_range);
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bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
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struct mlx5_rate_limit *rl_1)
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{
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return ((rl_0->rate == rl_1->rate) &&
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(rl_0->max_burst_sz == rl_1->max_burst_sz) &&
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(rl_0->typical_pkt_sz == rl_1->typical_pkt_sz));
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}
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EXPORT_SYMBOL(mlx5_rl_are_equal);
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int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
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bool dedicated_entry, u16 *index)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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struct mlx5_rl_entry *entry;
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int err = 0;
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u32 rate;
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rate = MLX5_GET(set_pp_rate_limit_context, rl_in, rate_limit);
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mutex_lock(&table->rl_lock);
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if (!rate || !mlx5_rl_is_in_range(dev, rate)) {
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mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
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rate, table->min_rate, table->max_rate);
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err = -EINVAL;
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goto out;
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}
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entry = find_rl_entry(table, rl_in, uid, dedicated_entry);
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if (!entry) {
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mlx5_core_err(dev, "Max number of %u rates reached\n",
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table->max_size);
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err = -ENOSPC;
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goto out;
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}
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if (entry->refcount) {
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/* rate already configured */
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entry->refcount++;
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} else {
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memcpy(entry->rl_raw, rl_in, sizeof(entry->rl_raw));
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entry->uid = uid;
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/* new rate limit */
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err = mlx5_set_pp_rate_limit_cmd(dev, entry, true);
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if (err) {
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mlx5_core_err(
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dev,
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"Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
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err, rate,
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MLX5_GET(set_pp_rate_limit_context, rl_in,
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burst_upper_bound),
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MLX5_GET(set_pp_rate_limit_context, rl_in,
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typical_packet_size));
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goto out;
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}
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entry->refcount = 1;
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entry->dedicated = dedicated_entry;
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}
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*index = entry->index;
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out:
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mutex_unlock(&table->rl_lock);
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return err;
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}
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EXPORT_SYMBOL(mlx5_rl_add_rate_raw);
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void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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struct mlx5_rl_entry *entry;
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mutex_lock(&table->rl_lock);
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entry = &table->rl_entry[index - 1];
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entry->refcount--;
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if (!entry->refcount)
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/* need to remove rate */
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mlx5_set_pp_rate_limit_cmd(dev, entry, false);
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mutex_unlock(&table->rl_lock);
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}
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EXPORT_SYMBOL(mlx5_rl_remove_rate_raw);
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int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
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struct mlx5_rate_limit *rl)
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{
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u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
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MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
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rl->max_burst_sz);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
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rl->typical_pkt_sz);
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return mlx5_rl_add_rate_raw(dev, rl_raw,
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MLX5_CAP_QOS(dev, packet_pacing_uid) ?
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MLX5_SHARED_RESOURCE_UID : 0,
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false, index);
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}
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EXPORT_SYMBOL(mlx5_rl_add_rate);
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void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
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{
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u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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struct mlx5_rl_entry *entry = NULL;
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/* 0 is a reserved value for unlimited rate */
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if (rl->rate == 0)
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return;
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MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
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rl->max_burst_sz);
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MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
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rl->typical_pkt_sz);
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mutex_lock(&table->rl_lock);
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entry = find_rl_entry(table, rl_raw,
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MLX5_CAP_QOS(dev, packet_pacing_uid) ?
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MLX5_SHARED_RESOURCE_UID : 0, false);
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if (!entry || !entry->refcount) {
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mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u are not configured\n",
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rl->rate, rl->max_burst_sz, rl->typical_pkt_sz);
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goto out;
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}
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entry->refcount--;
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if (!entry->refcount)
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/* need to remove rate */
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mlx5_set_pp_rate_limit_cmd(dev, entry, false);
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out:
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mutex_unlock(&table->rl_lock);
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}
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EXPORT_SYMBOL(mlx5_rl_remove_rate);
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int mlx5_init_rl_table(struct mlx5_core_dev *dev)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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int i;
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mutex_init(&table->rl_lock);
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if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) {
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table->max_size = 0;
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return 0;
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}
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/* First entry is reserved for unlimited rate */
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table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1;
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table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
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table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);
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table->rl_entry = kcalloc(table->max_size, sizeof(struct mlx5_rl_entry),
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GFP_KERNEL);
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if (!table->rl_entry)
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return -ENOMEM;
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/* The index represents the index in HW rate limit table
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* Index 0 is reserved for unlimited rate
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*/
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for (i = 0; i < table->max_size; i++)
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table->rl_entry[i].index = i + 1;
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/* Index 0 is reserved */
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mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
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table->max_size,
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table->min_rate >> 10,
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table->max_rate >> 10);
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return 0;
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}
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void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
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{
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struct mlx5_rl_table *table = &dev->priv.rl_table;
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int i;
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/* Clear all configured rates */
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for (i = 0; i < table->max_size; i++)
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if (table->rl_entry[i].refcount)
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mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i],
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false);
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kfree(dev->priv.rl_table.rl_entry);
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}
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