/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/mlx5/port.h>
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#include "mlx5_core.h"
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int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
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int size_in, void *data_out, int size_out,
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u16 reg_id, int arg, int write)
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{
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int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
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int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
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int err = -ENOMEM;
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u32 *out = NULL;
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u32 *in = NULL;
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void *data;
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in = kvzalloc(inlen, GFP_KERNEL);
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out = kvzalloc(outlen, GFP_KERNEL);
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if (!in || !out)
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goto out;
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data = MLX5_ADDR_OF(access_register_in, in, register_data);
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memcpy(data, data_in, size_in);
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MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
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MLX5_SET(access_register_in, in, op_mod, !write);
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MLX5_SET(access_register_in, in, argument, arg);
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MLX5_SET(access_register_in, in, register_id, reg_id);
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err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
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if (err)
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goto out;
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data = MLX5_ADDR_OF(access_register_out, out, register_data);
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memcpy(data_out, data, size_out);
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out:
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kvfree(out);
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kvfree(in);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
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int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
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u8 access_reg_group)
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{
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u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
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int sz = MLX5_ST_SZ_BYTES(pcam_reg);
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MLX5_SET(pcam_reg, in, feature_group, feature_group);
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MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
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return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
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}
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int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
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u8 access_reg_group)
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{
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u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
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int sz = MLX5_ST_SZ_BYTES(mcam_reg);
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MLX5_SET(mcam_reg, in, feature_group, feature_group);
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MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
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return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
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}
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int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
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u8 feature_group, u8 access_reg_group)
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{
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u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
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int sz = MLX5_ST_SZ_BYTES(qcam_reg);
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MLX5_SET(qcam_reg, in, feature_group, feature_group);
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MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
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return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
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}
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struct mlx5_reg_pcap {
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u8 rsvd0;
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u8 port_num;
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u8 rsvd1[2];
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__be32 caps_127_96;
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__be32 caps_95_64;
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__be32 caps_63_32;
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__be32 caps_31_0;
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};
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int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
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{
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struct mlx5_reg_pcap in;
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struct mlx5_reg_pcap out;
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memset(&in, 0, sizeof(in));
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in.caps_127_96 = cpu_to_be32(caps);
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in.port_num = port_num;
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return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
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sizeof(out), MLX5_REG_PCAP, 0, 1);
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
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int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
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int ptys_size, int proto_mask, u8 local_port)
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{
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u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
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MLX5_SET(ptys_reg, in, local_port, local_port);
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MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
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return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
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ptys_size, MLX5_REG_PTYS, 0, 0);
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
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int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
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{
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u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
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u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
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MLX5_SET(mlcr_reg, in, local_port, 1);
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MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
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return mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_MLCR, 0, 1);
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}
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int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
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u16 *proto_oper, u8 local_port)
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{
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u32 out[MLX5_ST_SZ_DW(ptys_reg)];
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int err;
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err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
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local_port);
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if (err)
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return err;
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*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
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*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
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return 0;
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}
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EXPORT_SYMBOL(mlx5_query_ib_port_oper);
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/* This function should be used after setting a port register only */
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void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
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{
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enum mlx5_port_status ps;
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mlx5_query_port_admin_status(dev, &ps);
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mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
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if (ps == MLX5_PORT_UP)
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mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
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}
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EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
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int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
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enum mlx5_port_status status)
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{
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u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
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u32 out[MLX5_ST_SZ_DW(paos_reg)];
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MLX5_SET(paos_reg, in, local_port, 1);
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MLX5_SET(paos_reg, in, admin_status, status);
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MLX5_SET(paos_reg, in, ase, 1);
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return mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_PAOS, 0, 1);
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
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int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
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enum mlx5_port_status *status)
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{
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u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
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u32 out[MLX5_ST_SZ_DW(paos_reg)];
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int err;
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MLX5_SET(paos_reg, in, local_port, 1);
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err = mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_PAOS, 0, 0);
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if (err)
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return err;
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*status = MLX5_GET(paos_reg, out, admin_status);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
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static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
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u16 *max_mtu, u16 *oper_mtu, u8 port)
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{
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u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
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u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
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MLX5_SET(pmtu_reg, in, local_port, port);
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mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_PMTU, 0, 0);
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if (max_mtu)
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*max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
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if (oper_mtu)
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*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
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if (admin_mtu)
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*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
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}
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int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
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{
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u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
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u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
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MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
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MLX5_SET(pmtu_reg, in, local_port, port);
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return mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_PMTU, 0, 1);
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
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void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
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u8 port)
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{
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mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
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void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
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u8 port)
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{
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mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
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static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
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{
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u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
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u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
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int module_mapping;
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int err;
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MLX5_SET(pmlp_reg, in, local_port, 1);
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err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
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MLX5_REG_PMLP, 0, 0);
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if (err)
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return err;
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module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
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*module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
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return 0;
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}
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static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num,
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u8 *module_id)
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{
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u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
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u32 out[MLX5_ST_SZ_DW(mcia_reg)];
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int err, status;
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u8 *ptr;
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MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW);
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MLX5_SET(mcia_reg, in, module, module_num);
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MLX5_SET(mcia_reg, in, device_address, 0);
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MLX5_SET(mcia_reg, in, page_number, 0);
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MLX5_SET(mcia_reg, in, size, 1);
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MLX5_SET(mcia_reg, in, l, 0);
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err = mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_MCIA, 0, 0);
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if (err)
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return err;
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status = MLX5_GET(mcia_reg, out, status);
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if (status) {
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mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
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status);
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return -EIO;
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}
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ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
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*module_id = ptr[0];
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return 0;
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}
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static int mlx5_qsfp_eeprom_page(u16 offset)
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{
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if (offset < MLX5_EEPROM_PAGE_LENGTH)
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/* Addresses between 0-255 - page 00 */
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return 0;
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/* Addresses between 256 - 639 belongs to pages 01, 02 and 03
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* For example, offset = 400 belongs to page 02:
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* 1 + ((400 - 256)/128) = 2
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*/
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return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) /
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MLX5_EEPROM_HIGH_PAGE_LENGTH);
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}
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static int mlx5_qsfp_eeprom_high_page_offset(int page_num)
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{
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if (!page_num) /* Page 0 always start from low page */
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return 0;
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/* High page */
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return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH;
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}
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static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
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{
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*i2c_addr = MLX5_I2C_ADDR_LOW;
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*page_num = mlx5_qsfp_eeprom_page(*offset);
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*offset -= mlx5_qsfp_eeprom_high_page_offset(*page_num);
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}
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static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
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{
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*i2c_addr = MLX5_I2C_ADDR_LOW;
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*page_num = 0;
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if (*offset < MLX5_EEPROM_PAGE_LENGTH)
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return;
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*i2c_addr = MLX5_I2C_ADDR_HIGH;
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*offset -= MLX5_EEPROM_PAGE_LENGTH;
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}
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int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
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u16 offset, u16 size, u8 *data)
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{
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int module_num, status, err, page_num = 0;
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u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
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u32 out[MLX5_ST_SZ_DW(mcia_reg)];
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u16 i2c_addr = 0;
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u8 module_id;
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void *ptr;
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err = mlx5_query_module_num(dev, &module_num);
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if (err)
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return err;
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err = mlx5_query_module_id(dev, module_num, &module_id);
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if (err)
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return err;
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switch (module_id) {
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case MLX5_MODULE_ID_SFP:
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mlx5_sfp_eeprom_params_set(&i2c_addr, &page_num, &offset);
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break;
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case MLX5_MODULE_ID_QSFP:
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case MLX5_MODULE_ID_QSFP_PLUS:
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case MLX5_MODULE_ID_QSFP28:
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mlx5_qsfp_eeprom_params_set(&i2c_addr, &page_num, &offset);
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break;
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default:
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mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id);
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return -EINVAL;
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}
|
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if (offset + size > MLX5_EEPROM_PAGE_LENGTH)
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/* Cross pages read, read until offset 256 in low page */
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size -= offset + size - MLX5_EEPROM_PAGE_LENGTH;
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size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
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MLX5_SET(mcia_reg, in, l, 0);
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MLX5_SET(mcia_reg, in, module, module_num);
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MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
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MLX5_SET(mcia_reg, in, page_number, page_num);
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MLX5_SET(mcia_reg, in, device_address, offset);
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MLX5_SET(mcia_reg, in, size, size);
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err = mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_MCIA, 0, 0);
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if (err)
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return err;
|
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status = MLX5_GET(mcia_reg, out, status);
|
if (status) {
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mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
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status);
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return -EIO;
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}
|
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ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
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memcpy(data, ptr, size);
|
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return size;
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}
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EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
|
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static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
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int pvlc_size, u8 local_port)
|
{
|
u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
|
|
MLX5_SET(pvlc_reg, in, local_port, local_port);
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return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
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pvlc_size, MLX5_REG_PVLC, 0, 0);
|
}
|
|
int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
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u8 *vl_hw_cap, u8 local_port)
|
{
|
u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
|
int err;
|
|
err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
|
if (err)
|
return err;
|
|
*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
|
|
return 0;
|
}
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EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
|
|
int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
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u8 port_num, void *out, size_t sz)
|
{
|
u32 *in;
|
int err;
|
|
in = kvzalloc(sz, GFP_KERNEL);
|
if (!in) {
|
err = -ENOMEM;
|
return err;
|
}
|
|
MLX5_SET(ppcnt_reg, in, local_port, port_num);
|
|
MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
|
err = mlx5_core_access_reg(dev, in, sz, out,
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sz, MLX5_REG_PPCNT, 0, 0);
|
|
kvfree(in);
|
return err;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
|
|
static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
|
u32 out_size)
|
{
|
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
|
|
MLX5_SET(pfcc_reg, in, local_port, 1);
|
|
return mlx5_core_access_reg(dev, in, sizeof(in), out,
|
out_size, MLX5_REG_PFCC, 0, 0);
|
}
|
|
int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
|
{
|
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
|
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
|
|
MLX5_SET(pfcc_reg, in, local_port, 1);
|
MLX5_SET(pfcc_reg, in, pptx, tx_pause);
|
MLX5_SET(pfcc_reg, in, pprx, rx_pause);
|
|
return mlx5_core_access_reg(dev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_PFCC, 0, 1);
|
}
|
EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
|
|
int mlx5_query_port_pause(struct mlx5_core_dev *dev,
|
u32 *rx_pause, u32 *tx_pause)
|
{
|
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
|
int err;
|
|
err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
|
if (err)
|
return err;
|
|
if (rx_pause)
|
*rx_pause = MLX5_GET(pfcc_reg, out, pprx);
|
|
if (tx_pause)
|
*tx_pause = MLX5_GET(pfcc_reg, out, pptx);
|
|
return 0;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
|
|
int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
|
u16 stall_critical_watermark,
|
u16 stall_minor_watermark)
|
{
|
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
|
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
|
|
MLX5_SET(pfcc_reg, in, local_port, 1);
|
MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
|
MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
|
MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
|
MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
|
MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
|
MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
|
stall_critical_watermark);
|
MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
|
|
return mlx5_core_access_reg(dev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_PFCC, 0, 1);
|
}
|
|
int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
|
u16 *stall_critical_watermark,
|
u16 *stall_minor_watermark)
|
{
|
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
|
int err;
|
|
err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
|
if (err)
|
return err;
|
|
if (stall_critical_watermark)
|
*stall_critical_watermark = MLX5_GET(pfcc_reg, out,
|
device_stall_critical_watermark);
|
|
if (stall_minor_watermark)
|
*stall_minor_watermark = MLX5_GET(pfcc_reg, out,
|
device_stall_minor_watermark);
|
|
return 0;
|
}
|
|
int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
|
{
|
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
|
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
|
|
MLX5_SET(pfcc_reg, in, local_port, 1);
|
MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
|
MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
|
MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
|
MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
|
|
return mlx5_core_access_reg(dev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_PFCC, 0, 1);
|
}
|
EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
|
|
int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
|
{
|
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
|
int err;
|
|
err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
|
if (err)
|
return err;
|
|
if (pfc_en_tx)
|
*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
|
|
if (pfc_en_rx)
|
*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
|
|
return 0;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
|
|
int mlx5_max_tc(struct mlx5_core_dev *mdev)
|
{
|
u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
|
|
return num_tc - 1;
|
}
|
|
int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
|
{
|
u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
|
|
MLX5_SET(dcbx_param, in, port_number, 1);
|
|
return mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
|
}
|
|
int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
|
{
|
u32 out[MLX5_ST_SZ_DW(dcbx_param)];
|
|
MLX5_SET(dcbx_param, in, port_number, 1);
|
|
return mlx5_core_access_reg(mdev, in, sizeof(out), out,
|
sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
|
}
|
|
int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
|
{
|
u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
|
u32 out[MLX5_ST_SZ_DW(qtct_reg)];
|
int err;
|
int i;
|
|
for (i = 0; i < 8; i++) {
|
if (prio_tc[i] > mlx5_max_tc(mdev))
|
return -EINVAL;
|
|
MLX5_SET(qtct_reg, in, prio, i);
|
MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
|
|
err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_QTCT, 0, 1);
|
if (err)
|
return err;
|
}
|
|
return 0;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
|
|
int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
|
u8 prio, u8 *tc)
|
{
|
u32 in[MLX5_ST_SZ_DW(qtct_reg)];
|
u32 out[MLX5_ST_SZ_DW(qtct_reg)];
|
int err;
|
|
memset(in, 0, sizeof(in));
|
memset(out, 0, sizeof(out));
|
|
MLX5_SET(qtct_reg, in, port_number, 1);
|
MLX5_SET(qtct_reg, in, prio, prio);
|
|
err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_QTCT, 0, 0);
|
if (!err)
|
*tc = MLX5_GET(qtct_reg, out, tclass);
|
|
return err;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
|
|
static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
|
int inlen)
|
{
|
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
|
|
if (!MLX5_CAP_GEN(mdev, ets))
|
return -EOPNOTSUPP;
|
|
return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
|
MLX5_REG_QETCR, 0, 1);
|
}
|
|
static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
|
int outlen)
|
{
|
u32 in[MLX5_ST_SZ_DW(qetc_reg)];
|
|
if (!MLX5_CAP_GEN(mdev, ets))
|
return -EOPNOTSUPP;
|
|
memset(in, 0, sizeof(in));
|
return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
|
MLX5_REG_QETCR, 0, 0);
|
}
|
|
int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
|
{
|
u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
|
int i;
|
|
for (i = 0; i <= mlx5_max_tc(mdev); i++) {
|
MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
|
MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
|
}
|
|
return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
|
}
|
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
|
|
int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
|
u8 tc, u8 *tc_group)
|
{
|
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
|
void *ets_tcn_conf;
|
int err;
|
|
err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
|
if (err)
|
return err;
|
|
ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
|
tc_configuration[tc]);
|
|
*tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
|
group);
|
|
return 0;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
|
|
int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
|
{
|
u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
|
int i;
|
|
for (i = 0; i <= mlx5_max_tc(mdev); i++) {
|
MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
|
MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
|
}
|
|
return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
|
}
|
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
|
|
int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
|
u8 tc, u8 *bw_pct)
|
{
|
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
|
void *ets_tcn_conf;
|
int err;
|
|
err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
|
if (err)
|
return err;
|
|
ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
|
tc_configuration[tc]);
|
|
*bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
|
bw_allocation);
|
|
return 0;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
|
|
int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
|
u8 *max_bw_value,
|
u8 *max_bw_units)
|
{
|
u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
|
void *ets_tcn_conf;
|
int i;
|
|
MLX5_SET(qetc_reg, in, port_number, 1);
|
|
for (i = 0; i <= mlx5_max_tc(mdev); i++) {
|
ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
|
|
MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
|
MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
|
max_bw_units[i]);
|
MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
|
max_bw_value[i]);
|
}
|
|
return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
|
}
|
EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
|
|
int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
|
u8 *max_bw_value,
|
u8 *max_bw_units)
|
{
|
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
|
void *ets_tcn_conf;
|
int err;
|
int i;
|
|
err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
|
if (err)
|
return err;
|
|
for (i = 0; i <= mlx5_max_tc(mdev); i++) {
|
ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
|
|
max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
|
max_bw_value);
|
max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
|
max_bw_units);
|
}
|
|
return 0;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
|
|
int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
|
{
|
u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {};
|
|
MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
|
MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
|
MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
|
return mlx5_cmd_exec_in(mdev, set_wol_rol, in);
|
}
|
EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
|
|
int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
|
{
|
u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {};
|
u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {};
|
int err;
|
|
MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
|
err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out);
|
if (!err)
|
*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
|
|
return err;
|
}
|
EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
|
|
int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
|
{
|
u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
|
|
MLX5_SET(pcmr_reg, in, local_port, 1);
|
return mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
outlen, MLX5_REG_PCMR, 0, 0);
|
}
|
|
int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
|
{
|
u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
|
|
return mlx5_core_access_reg(mdev, in, inlen, out,
|
sizeof(out), MLX5_REG_PCMR, 0, 1);
|
}
|
|
int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
|
{
|
u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
|
int err;
|
|
err = mlx5_query_ports_check(mdev, in, sizeof(in));
|
if (err)
|
return err;
|
MLX5_SET(pcmr_reg, in, local_port, 1);
|
MLX5_SET(pcmr_reg, in, fcs_chk, enable);
|
return mlx5_set_ports_check(mdev, in, sizeof(in));
|
}
|
|
void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
|
bool *enabled)
|
{
|
u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
|
/* Default values for FW which do not support MLX5_REG_PCMR */
|
*supported = false;
|
*enabled = true;
|
|
if (!MLX5_CAP_GEN(mdev, ports_check))
|
return;
|
|
if (mlx5_query_ports_check(mdev, out, sizeof(out)))
|
return;
|
|
*supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
|
*enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
|
}
|
|
int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
|
{
|
u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
|
|
return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
|
mtpps_size, MLX5_REG_MTPPS, 0, 0);
|
}
|
|
int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
|
{
|
u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
|
|
return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
|
sizeof(out), MLX5_REG_MTPPS, 0, 1);
|
}
|
|
int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
|
{
|
u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
|
u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
|
int err = 0;
|
|
MLX5_SET(mtppse_reg, in, pin, pin);
|
|
err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_MTPPSE, 0, 0);
|
if (err)
|
return err;
|
|
*arm = MLX5_GET(mtppse_reg, in, event_arm);
|
*mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
|
|
return err;
|
}
|
|
int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
|
{
|
u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
|
u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
|
|
MLX5_SET(mtppse_reg, in, pin, pin);
|
MLX5_SET(mtppse_reg, in, event_arm, arm);
|
MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
|
|
return mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_MTPPSE, 0, 1);
|
}
|
|
int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
|
{
|
u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
|
u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
|
int err;
|
|
MLX5_SET(qpts_reg, in, local_port, 1);
|
MLX5_SET(qpts_reg, in, trust_state, trust_state);
|
|
err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_QPTS, 0, 1);
|
return err;
|
}
|
|
int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
|
{
|
u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
|
u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
|
int err;
|
|
MLX5_SET(qpts_reg, in, local_port, 1);
|
|
err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
|
sizeof(out), MLX5_REG_QPTS, 0, 0);
|
if (!err)
|
*trust_state = MLX5_GET(qpts_reg, out, trust_state);
|
|
return err;
|
}
|
|
int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
|
{
|
int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
|
void *qpdpm_dscp;
|
void *out;
|
void *in;
|
int err;
|
|
in = kzalloc(sz, GFP_KERNEL);
|
out = kzalloc(sz, GFP_KERNEL);
|
if (!in || !out) {
|
err = -ENOMEM;
|
goto out;
|
}
|
|
MLX5_SET(qpdpm_reg, in, local_port, 1);
|
err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
|
if (err)
|
goto out;
|
|
memcpy(in, out, sz);
|
MLX5_SET(qpdpm_reg, in, local_port, 1);
|
|
/* Update the corresponding dscp entry */
|
qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
|
MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
|
MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
|
err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
|
|
out:
|
kfree(in);
|
kfree(out);
|
return err;
|
}
|
|
/* dscp2prio[i]: priority that dscp i mapped to */
|
#define MLX5E_SUPPORTED_DSCP 64
|
int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
|
{
|
int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
|
void *qpdpm_dscp;
|
void *out;
|
void *in;
|
int err;
|
int i;
|
|
in = kzalloc(sz, GFP_KERNEL);
|
out = kzalloc(sz, GFP_KERNEL);
|
if (!in || !out) {
|
err = -ENOMEM;
|
goto out;
|
}
|
|
MLX5_SET(qpdpm_reg, in, local_port, 1);
|
err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
|
if (err)
|
goto out;
|
|
for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
|
qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
|
dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
|
}
|
|
out:
|
kfree(in);
|
kfree(out);
|
return err;
|
}
|
