/*
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* Copyright (c) 2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/clocksource.h>
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#include <linux/highmem.h>
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#include <linux/ptp_clock_kernel.h>
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#include <rdma/mlx5-abi.h>
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#include "lib/eq.h"
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#include "en.h"
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#include "clock.h"
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enum {
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MLX5_CYCLES_SHIFT = 23
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};
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enum {
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MLX5_PIN_MODE_IN = 0x0,
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MLX5_PIN_MODE_OUT = 0x1,
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};
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enum {
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MLX5_OUT_PATTERN_PULSE = 0x0,
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MLX5_OUT_PATTERN_PERIODIC = 0x1,
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};
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enum {
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MLX5_EVENT_MODE_DISABLE = 0x0,
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MLX5_EVENT_MODE_REPETETIVE = 0x1,
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MLX5_EVENT_MODE_ONCE_TILL_ARM = 0x2,
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};
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enum {
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MLX5_MTPPS_FS_ENABLE = BIT(0x0),
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MLX5_MTPPS_FS_PATTERN = BIT(0x2),
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MLX5_MTPPS_FS_PIN_MODE = BIT(0x3),
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MLX5_MTPPS_FS_TIME_STAMP = BIT(0x4),
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MLX5_MTPPS_FS_OUT_PULSE_DURATION = BIT(0x5),
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MLX5_MTPPS_FS_ENH_OUT_PER_ADJ = BIT(0x7),
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};
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static u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
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struct ptp_system_timestamp *sts)
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{
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u32 timer_h, timer_h1, timer_l;
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timer_h = ioread32be(&dev->iseg->internal_timer_h);
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ptp_read_system_prets(sts);
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timer_l = ioread32be(&dev->iseg->internal_timer_l);
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ptp_read_system_postts(sts);
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timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
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if (timer_h != timer_h1) {
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/* wrap around */
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ptp_read_system_prets(sts);
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timer_l = ioread32be(&dev->iseg->internal_timer_l);
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ptp_read_system_postts(sts);
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}
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return (u64)timer_l | (u64)timer_h1 << 32;
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}
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static u64 read_internal_timer(const struct cyclecounter *cc)
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{
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struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles);
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struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer);
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struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev,
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clock);
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return mlx5_read_internal_timer(mdev, NULL) & cc->mask;
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}
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static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev)
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{
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struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
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struct mlx5_clock *clock = &mdev->clock;
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struct mlx5_timer *timer;
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u32 sign;
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if (!clock_info)
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return;
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sign = smp_load_acquire(&clock_info->sign);
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smp_store_mb(clock_info->sign,
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sign | MLX5_IB_CLOCK_INFO_KERNEL_UPDATING);
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timer = &clock->timer;
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clock_info->cycles = timer->tc.cycle_last;
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clock_info->mult = timer->cycles.mult;
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clock_info->nsec = timer->tc.nsec;
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clock_info->frac = timer->tc.frac;
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smp_store_release(&clock_info->sign,
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sign + MLX5_IB_CLOCK_INFO_KERNEL_UPDATING * 2);
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}
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static void mlx5_pps_out(struct work_struct *work)
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{
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struct mlx5_pps *pps_info = container_of(work, struct mlx5_pps,
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out_work);
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struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock,
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pps_info);
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struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev,
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clock);
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u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
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unsigned long flags;
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int i;
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for (i = 0; i < clock->ptp_info.n_pins; i++) {
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u64 tstart;
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write_seqlock_irqsave(&clock->lock, flags);
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tstart = clock->pps_info.start[i];
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clock->pps_info.start[i] = 0;
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write_sequnlock_irqrestore(&clock->lock, flags);
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if (!tstart)
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continue;
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MLX5_SET(mtpps_reg, in, pin, i);
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MLX5_SET64(mtpps_reg, in, time_stamp, tstart);
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MLX5_SET(mtpps_reg, in, field_select, MLX5_MTPPS_FS_TIME_STAMP);
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mlx5_set_mtpps(mdev, in, sizeof(in));
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}
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}
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static void mlx5_timestamp_overflow(struct work_struct *work)
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{
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struct delayed_work *dwork = to_delayed_work(work);
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struct mlx5_core_dev *mdev;
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struct mlx5_timer *timer;
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struct mlx5_clock *clock;
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unsigned long flags;
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timer = container_of(dwork, struct mlx5_timer, overflow_work);
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clock = container_of(timer, struct mlx5_clock, timer);
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mdev = container_of(clock, struct mlx5_core_dev, clock);
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if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
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goto out;
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write_seqlock_irqsave(&clock->lock, flags);
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timecounter_read(&timer->tc);
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mlx5_update_clock_info_page(mdev);
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write_sequnlock_irqrestore(&clock->lock, flags);
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out:
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schedule_delayed_work(&timer->overflow_work, timer->overflow_period);
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}
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static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts)
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{
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struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
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struct mlx5_timer *timer = &clock->timer;
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u64 ns = timespec64_to_ns(ts);
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struct mlx5_core_dev *mdev;
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unsigned long flags;
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mdev = container_of(clock, struct mlx5_core_dev, clock);
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write_seqlock_irqsave(&clock->lock, flags);
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timecounter_init(&timer->tc, &timer->cycles, ns);
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mlx5_update_clock_info_page(mdev);
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write_sequnlock_irqrestore(&clock->lock, flags);
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return 0;
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}
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static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
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struct ptp_system_timestamp *sts)
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{
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struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
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struct mlx5_timer *timer = &clock->timer;
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struct mlx5_core_dev *mdev;
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unsigned long flags;
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u64 cycles, ns;
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mdev = container_of(clock, struct mlx5_core_dev, clock);
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write_seqlock_irqsave(&clock->lock, flags);
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cycles = mlx5_read_internal_timer(mdev, sts);
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ns = timecounter_cyc2time(&timer->tc, cycles);
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write_sequnlock_irqrestore(&clock->lock, flags);
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*ts = ns_to_timespec64(ns);
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return 0;
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}
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static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
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struct mlx5_timer *timer = &clock->timer;
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struct mlx5_core_dev *mdev;
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unsigned long flags;
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mdev = container_of(clock, struct mlx5_core_dev, clock);
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write_seqlock_irqsave(&clock->lock, flags);
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timecounter_adjtime(&timer->tc, delta);
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mlx5_update_clock_info_page(mdev);
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write_sequnlock_irqrestore(&clock->lock, flags);
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return 0;
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}
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static int mlx5_ptp_adjfreq(struct ptp_clock_info *ptp, s32 delta)
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{
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struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info);
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struct mlx5_timer *timer = &clock->timer;
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struct mlx5_core_dev *mdev;
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unsigned long flags;
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int neg_adj = 0;
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u32 diff;
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u64 adj;
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if (delta < 0) {
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neg_adj = 1;
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delta = -delta;
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}
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adj = timer->nominal_c_mult;
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adj *= delta;
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diff = div_u64(adj, 1000000000ULL);
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mdev = container_of(clock, struct mlx5_core_dev, clock);
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write_seqlock_irqsave(&clock->lock, flags);
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timecounter_read(&timer->tc);
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timer->cycles.mult = neg_adj ? timer->nominal_c_mult - diff :
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timer->nominal_c_mult + diff;
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mlx5_update_clock_info_page(mdev);
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write_sequnlock_irqrestore(&clock->lock, flags);
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return 0;
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}
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static int mlx5_extts_configure(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq,
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int on)
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{
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struct mlx5_clock *clock =
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container_of(ptp, struct mlx5_clock, ptp_info);
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struct mlx5_core_dev *mdev =
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container_of(clock, struct mlx5_core_dev, clock);
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u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
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u32 field_select = 0;
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u8 pin_mode = 0;
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u8 pattern = 0;
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int pin = -1;
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int err = 0;
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if (!MLX5_PPS_CAP(mdev))
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return -EOPNOTSUPP;
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/* Reject requests with unsupported flags */
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if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
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PTP_RISING_EDGE |
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PTP_FALLING_EDGE |
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PTP_STRICT_FLAGS))
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return -EOPNOTSUPP;
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/* Reject requests to enable time stamping on both edges. */
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if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
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(rq->extts.flags & PTP_ENABLE_FEATURE) &&
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(rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
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return -EOPNOTSUPP;
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if (rq->extts.index >= clock->ptp_info.n_pins)
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return -EINVAL;
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pin = ptp_find_pin(clock->ptp, PTP_PF_EXTTS, rq->extts.index);
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if (pin < 0)
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return -EBUSY;
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if (on) {
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pin_mode = MLX5_PIN_MODE_IN;
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pattern = !!(rq->extts.flags & PTP_FALLING_EDGE);
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field_select = MLX5_MTPPS_FS_PIN_MODE |
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MLX5_MTPPS_FS_PATTERN |
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MLX5_MTPPS_FS_ENABLE;
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} else {
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field_select = MLX5_MTPPS_FS_ENABLE;
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}
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MLX5_SET(mtpps_reg, in, pin, pin);
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MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
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MLX5_SET(mtpps_reg, in, pattern, pattern);
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MLX5_SET(mtpps_reg, in, enable, on);
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MLX5_SET(mtpps_reg, in, field_select, field_select);
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err = mlx5_set_mtpps(mdev, in, sizeof(in));
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if (err)
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return err;
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return mlx5_set_mtppse(mdev, pin, 0,
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MLX5_EVENT_MODE_REPETETIVE & on);
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}
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static int mlx5_perout_configure(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq,
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int on)
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{
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struct mlx5_clock *clock =
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container_of(ptp, struct mlx5_clock, ptp_info);
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struct mlx5_core_dev *mdev =
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container_of(clock, struct mlx5_core_dev, clock);
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struct mlx5_timer *timer = &clock->timer;
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u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
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u64 nsec_now, nsec_delta, time_stamp = 0;
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u64 cycles_now, cycles_delta;
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struct timespec64 ts;
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unsigned long flags;
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u32 field_select = 0;
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u8 pin_mode = 0;
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u8 pattern = 0;
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int pin = -1;
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int err = 0;
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s64 ns;
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if (!MLX5_PPS_CAP(mdev))
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return -EOPNOTSUPP;
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/* Reject requests with unsupported flags */
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if (rq->perout.flags)
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return -EOPNOTSUPP;
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if (rq->perout.index >= clock->ptp_info.n_pins)
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return -EINVAL;
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pin = ptp_find_pin(clock->ptp, PTP_PF_PEROUT,
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rq->perout.index);
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if (pin < 0)
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return -EBUSY;
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if (on) {
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pin_mode = MLX5_PIN_MODE_OUT;
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pattern = MLX5_OUT_PATTERN_PERIODIC;
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ts.tv_sec = rq->perout.period.sec;
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ts.tv_nsec = rq->perout.period.nsec;
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ns = timespec64_to_ns(&ts);
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if ((ns >> 1) != 500000000LL)
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return -EINVAL;
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ts.tv_sec = rq->perout.start.sec;
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ts.tv_nsec = rq->perout.start.nsec;
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ns = timespec64_to_ns(&ts);
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cycles_now = mlx5_read_internal_timer(mdev, NULL);
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write_seqlock_irqsave(&clock->lock, flags);
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nsec_now = timecounter_cyc2time(&timer->tc, cycles_now);
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nsec_delta = ns - nsec_now;
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cycles_delta = div64_u64(nsec_delta << timer->cycles.shift,
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timer->cycles.mult);
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write_sequnlock_irqrestore(&clock->lock, flags);
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time_stamp = cycles_now + cycles_delta;
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field_select = MLX5_MTPPS_FS_PIN_MODE |
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MLX5_MTPPS_FS_PATTERN |
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MLX5_MTPPS_FS_ENABLE |
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MLX5_MTPPS_FS_TIME_STAMP;
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} else {
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field_select = MLX5_MTPPS_FS_ENABLE;
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}
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MLX5_SET(mtpps_reg, in, pin, pin);
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MLX5_SET(mtpps_reg, in, pin_mode, pin_mode);
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MLX5_SET(mtpps_reg, in, pattern, pattern);
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MLX5_SET(mtpps_reg, in, enable, on);
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MLX5_SET64(mtpps_reg, in, time_stamp, time_stamp);
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MLX5_SET(mtpps_reg, in, field_select, field_select);
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err = mlx5_set_mtpps(mdev, in, sizeof(in));
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if (err)
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return err;
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return mlx5_set_mtppse(mdev, pin, 0,
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MLX5_EVENT_MODE_REPETETIVE & on);
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}
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static int mlx5_pps_configure(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq,
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int on)
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{
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struct mlx5_clock *clock =
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container_of(ptp, struct mlx5_clock, ptp_info);
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clock->pps_info.enabled = !!on;
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return 0;
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}
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static int mlx5_ptp_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq,
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int on)
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{
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switch (rq->type) {
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case PTP_CLK_REQ_EXTTS:
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return mlx5_extts_configure(ptp, rq, on);
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case PTP_CLK_REQ_PEROUT:
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return mlx5_perout_configure(ptp, rq, on);
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case PTP_CLK_REQ_PPS:
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return mlx5_pps_configure(ptp, rq, on);
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default:
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return -EOPNOTSUPP;
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}
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return 0;
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}
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enum {
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MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN = BIT(0),
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MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT = BIT(1),
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};
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static int mlx5_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan)
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{
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struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock,
|
ptp_info);
|
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switch (func) {
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case PTP_PF_NONE:
|
return 0;
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case PTP_PF_EXTTS:
|
return !(clock->pps_info.pin_caps[pin] &
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MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_IN);
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case PTP_PF_PEROUT:
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return !(clock->pps_info.pin_caps[pin] &
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MLX5_MTPPS_REG_CAP_PIN_X_MODE_SUPPORT_PPS_OUT);
|
default:
|
return -EOPNOTSUPP;
|
}
|
}
|
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static const struct ptp_clock_info mlx5_ptp_clock_info = {
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.owner = THIS_MODULE,
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.name = "mlx5_ptp",
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.max_adj = 50000000,
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.n_alarm = 0,
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.n_ext_ts = 0,
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.n_per_out = 0,
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.n_pins = 0,
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.pps = 0,
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.adjfreq = mlx5_ptp_adjfreq,
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.adjtime = mlx5_ptp_adjtime,
|
.gettimex64 = mlx5_ptp_gettimex,
|
.settime64 = mlx5_ptp_settime,
|
.enable = NULL,
|
.verify = NULL,
|
};
|
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static int mlx5_query_mtpps_pin_mode(struct mlx5_core_dev *mdev, u8 pin,
|
u32 *mtpps, u32 mtpps_size)
|
{
|
u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {};
|
|
MLX5_SET(mtpps_reg, in, pin, pin);
|
|
return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
|
mtpps_size, MLX5_REG_MTPPS, 0, 0);
|
}
|
|
static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin)
|
{
|
struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);
|
|
u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {};
|
u8 mode;
|
int err;
|
|
err = mlx5_query_mtpps_pin_mode(mdev, pin, out, sizeof(out));
|
if (err || !MLX5_GET(mtpps_reg, out, enable))
|
return PTP_PF_NONE;
|
|
mode = MLX5_GET(mtpps_reg, out, pin_mode);
|
|
if (mode == MLX5_PIN_MODE_IN)
|
return PTP_PF_EXTTS;
|
else if (mode == MLX5_PIN_MODE_OUT)
|
return PTP_PF_PEROUT;
|
|
return PTP_PF_NONE;
|
}
|
|
static int mlx5_init_pin_config(struct mlx5_clock *clock)
|
{
|
int i;
|
|
clock->ptp_info.pin_config =
|
kcalloc(clock->ptp_info.n_pins,
|
sizeof(*clock->ptp_info.pin_config),
|
GFP_KERNEL);
|
if (!clock->ptp_info.pin_config)
|
return -ENOMEM;
|
clock->ptp_info.enable = mlx5_ptp_enable;
|
clock->ptp_info.verify = mlx5_ptp_verify;
|
clock->ptp_info.pps = 1;
|
|
for (i = 0; i < clock->ptp_info.n_pins; i++) {
|
snprintf(clock->ptp_info.pin_config[i].name,
|
sizeof(clock->ptp_info.pin_config[i].name),
|
"mlx5_pps%d", i);
|
clock->ptp_info.pin_config[i].index = i;
|
clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(clock, i);
|
clock->ptp_info.pin_config[i].chan = 0;
|
}
|
|
return 0;
|
}
|
|
static void mlx5_get_pps_caps(struct mlx5_core_dev *mdev)
|
{
|
struct mlx5_clock *clock = &mdev->clock;
|
u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
|
|
mlx5_query_mtpps(mdev, out, sizeof(out));
|
|
clock->ptp_info.n_pins = MLX5_GET(mtpps_reg, out,
|
cap_number_of_pps_pins);
|
clock->ptp_info.n_ext_ts = MLX5_GET(mtpps_reg, out,
|
cap_max_num_of_pps_in_pins);
|
clock->ptp_info.n_per_out = MLX5_GET(mtpps_reg, out,
|
cap_max_num_of_pps_out_pins);
|
|
clock->pps_info.pin_caps[0] = MLX5_GET(mtpps_reg, out, cap_pin_0_mode);
|
clock->pps_info.pin_caps[1] = MLX5_GET(mtpps_reg, out, cap_pin_1_mode);
|
clock->pps_info.pin_caps[2] = MLX5_GET(mtpps_reg, out, cap_pin_2_mode);
|
clock->pps_info.pin_caps[3] = MLX5_GET(mtpps_reg, out, cap_pin_3_mode);
|
clock->pps_info.pin_caps[4] = MLX5_GET(mtpps_reg, out, cap_pin_4_mode);
|
clock->pps_info.pin_caps[5] = MLX5_GET(mtpps_reg, out, cap_pin_5_mode);
|
clock->pps_info.pin_caps[6] = MLX5_GET(mtpps_reg, out, cap_pin_6_mode);
|
clock->pps_info.pin_caps[7] = MLX5_GET(mtpps_reg, out, cap_pin_7_mode);
|
}
|
|
static int mlx5_pps_event(struct notifier_block *nb,
|
unsigned long type, void *data)
|
{
|
struct mlx5_clock *clock = mlx5_nb_cof(nb, struct mlx5_clock, pps_nb);
|
struct mlx5_timer *timer = &clock->timer;
|
struct ptp_clock_event ptp_event;
|
u64 cycles_now, cycles_delta;
|
u64 nsec_now, nsec_delta, ns;
|
struct mlx5_eqe *eqe = data;
|
int pin = eqe->data.pps.pin;
|
struct mlx5_core_dev *mdev;
|
struct timespec64 ts;
|
unsigned long flags;
|
|
mdev = container_of(clock, struct mlx5_core_dev, clock);
|
|
switch (clock->ptp_info.pin_config[pin].func) {
|
case PTP_PF_EXTTS:
|
ptp_event.index = pin;
|
ptp_event.timestamp =
|
mlx5_timecounter_cyc2time(clock,
|
be64_to_cpu(eqe->data.pps.time_stamp));
|
if (clock->pps_info.enabled) {
|
ptp_event.type = PTP_CLOCK_PPSUSR;
|
ptp_event.pps_times.ts_real =
|
ns_to_timespec64(ptp_event.timestamp);
|
} else {
|
ptp_event.type = PTP_CLOCK_EXTTS;
|
}
|
/* TODOL clock->ptp can be NULL if ptp_clock_register failes */
|
ptp_clock_event(clock->ptp, &ptp_event);
|
break;
|
case PTP_PF_PEROUT:
|
mlx5_ptp_gettimex(&clock->ptp_info, &ts, NULL);
|
cycles_now = mlx5_read_internal_timer(mdev, NULL);
|
ts.tv_sec += 1;
|
ts.tv_nsec = 0;
|
ns = timespec64_to_ns(&ts);
|
write_seqlock_irqsave(&clock->lock, flags);
|
nsec_now = timecounter_cyc2time(&timer->tc, cycles_now);
|
nsec_delta = ns - nsec_now;
|
cycles_delta = div64_u64(nsec_delta << timer->cycles.shift,
|
timer->cycles.mult);
|
clock->pps_info.start[pin] = cycles_now + cycles_delta;
|
write_sequnlock_irqrestore(&clock->lock, flags);
|
schedule_work(&clock->pps_info.out_work);
|
break;
|
default:
|
mlx5_core_err(mdev, " Unhandled clock PPS event, func %d\n",
|
clock->ptp_info.pin_config[pin].func);
|
}
|
|
return NOTIFY_OK;
|
}
|
|
static void mlx5_timecounter_init(struct mlx5_core_dev *mdev)
|
{
|
struct mlx5_clock *clock = &mdev->clock;
|
struct mlx5_timer *timer = &clock->timer;
|
u32 dev_freq;
|
|
dev_freq = MLX5_CAP_GEN(mdev, device_frequency_khz);
|
timer->cycles.read = read_internal_timer;
|
timer->cycles.shift = MLX5_CYCLES_SHIFT;
|
timer->cycles.mult = clocksource_khz2mult(dev_freq,
|
timer->cycles.shift);
|
timer->nominal_c_mult = timer->cycles.mult;
|
timer->cycles.mask = CLOCKSOURCE_MASK(41);
|
|
timecounter_init(&timer->tc, &timer->cycles,
|
ktime_to_ns(ktime_get_real()));
|
}
|
|
static void mlx5_init_overflow_period(struct mlx5_clock *clock)
|
{
|
struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock);
|
struct mlx5_ib_clock_info *clock_info = mdev->clock_info;
|
struct mlx5_timer *timer = &clock->timer;
|
u64 overflow_cycles;
|
u64 frac = 0;
|
u64 ns;
|
|
/* Calculate period in seconds to call the overflow watchdog - to make
|
* sure counter is checked at least twice every wrap around.
|
* The period is calculated as the minimum between max HW cycles count
|
* (The clock source mask) and max amount of cycles that can be
|
* multiplied by clock multiplier where the result doesn't exceed
|
* 64bits.
|
*/
|
overflow_cycles = div64_u64(~0ULL >> 1, timer->cycles.mult);
|
overflow_cycles = min(overflow_cycles, div_u64(timer->cycles.mask, 3));
|
|
ns = cyclecounter_cyc2ns(&timer->cycles, overflow_cycles,
|
frac, &frac);
|
do_div(ns, NSEC_PER_SEC / HZ);
|
timer->overflow_period = ns;
|
|
INIT_DELAYED_WORK(&timer->overflow_work, mlx5_timestamp_overflow);
|
if (timer->overflow_period)
|
schedule_delayed_work(&timer->overflow_work, 0);
|
else
|
mlx5_core_warn(mdev,
|
"invalid overflow period, overflow_work is not scheduled\n");
|
|
if (clock_info)
|
clock_info->overflow_period = timer->overflow_period;
|
}
|
|
static void mlx5_init_clock_info(struct mlx5_core_dev *mdev)
|
{
|
struct mlx5_clock *clock = &mdev->clock;
|
struct mlx5_ib_clock_info *info;
|
struct mlx5_timer *timer;
|
|
mdev->clock_info = (struct mlx5_ib_clock_info *)get_zeroed_page(GFP_KERNEL);
|
if (!mdev->clock_info) {
|
mlx5_core_warn(mdev, "Failed to allocate IB clock info page\n");
|
return;
|
}
|
|
info = mdev->clock_info;
|
timer = &clock->timer;
|
|
info->nsec = timer->tc.nsec;
|
info->cycles = timer->tc.cycle_last;
|
info->mask = timer->cycles.mask;
|
info->mult = timer->nominal_c_mult;
|
info->shift = timer->cycles.shift;
|
info->frac = timer->tc.frac;
|
}
|
|
void mlx5_init_clock(struct mlx5_core_dev *mdev)
|
{
|
struct mlx5_clock *clock = &mdev->clock;
|
|
if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) {
|
mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n");
|
return;
|
}
|
|
seqlock_init(&clock->lock);
|
|
mlx5_timecounter_init(mdev);
|
mlx5_init_clock_info(mdev);
|
mlx5_init_overflow_period(clock);
|
INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out);
|
|
/* Configure the PHC */
|
clock->ptp_info = mlx5_ptp_clock_info;
|
|
/* Initialize 1PPS data structures */
|
if (MLX5_PPS_CAP(mdev))
|
mlx5_get_pps_caps(mdev);
|
if (clock->ptp_info.n_pins)
|
mlx5_init_pin_config(clock);
|
|
clock->ptp = ptp_clock_register(&clock->ptp_info,
|
&mdev->pdev->dev);
|
if (IS_ERR(clock->ptp)) {
|
mlx5_core_warn(mdev, "ptp_clock_register failed %ld\n",
|
PTR_ERR(clock->ptp));
|
clock->ptp = NULL;
|
}
|
|
MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT);
|
mlx5_eq_notifier_register(mdev, &clock->pps_nb);
|
}
|
|
void mlx5_cleanup_clock(struct mlx5_core_dev *mdev)
|
{
|
struct mlx5_clock *clock = &mdev->clock;
|
|
if (!MLX5_CAP_GEN(mdev, device_frequency_khz))
|
return;
|
|
mlx5_eq_notifier_unregister(mdev, &clock->pps_nb);
|
if (clock->ptp) {
|
ptp_clock_unregister(clock->ptp);
|
clock->ptp = NULL;
|
}
|
|
cancel_work_sync(&clock->pps_info.out_work);
|
cancel_delayed_work_sync(&clock->timer.overflow_work);
|
|
if (mdev->clock_info) {
|
free_page((unsigned long)mdev->clock_info);
|
mdev->clock_info = NULL;
|
}
|
|
kfree(clock->ptp_info.pin_config);
|
}
|
