// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
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#include "fw_reset.h"
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#include "diag/fw_tracer.h"
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enum {
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MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
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MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
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MLX5_FW_RESET_FLAGS_PENDING_COMP
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};
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struct mlx5_fw_reset {
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struct mlx5_core_dev *dev;
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struct mlx5_nb nb;
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struct workqueue_struct *wq;
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struct work_struct fw_live_patch_work;
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struct work_struct reset_request_work;
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struct work_struct reset_reload_work;
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struct work_struct reset_now_work;
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struct work_struct reset_abort_work;
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unsigned long reset_flags;
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struct timer_list timer;
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struct completion done;
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int ret;
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};
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void mlx5_fw_reset_enable_remote_dev_reset_set(struct mlx5_core_dev *dev, bool enable)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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if (enable)
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clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
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else
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set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
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}
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bool mlx5_fw_reset_enable_remote_dev_reset_get(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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return !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
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}
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static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
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u8 reset_type_sel, u8 sync_resp, bool sync_start)
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{
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u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
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u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
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MLX5_SET(mfrl_reg, in, reset_level, reset_level);
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MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
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MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
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MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
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return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
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}
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static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
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{
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u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
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u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
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int err;
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err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
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if (err)
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return err;
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if (reset_level)
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*reset_level = MLX5_GET(mfrl_reg, out, reset_level);
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if (reset_type)
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*reset_type = MLX5_GET(mfrl_reg, out, reset_type);
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return 0;
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}
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int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
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{
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return mlx5_reg_mfrl_query(dev, reset_level, reset_type);
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}
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int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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int err;
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set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
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err = mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, reset_type_sel, 0, true);
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if (err)
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clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
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return err;
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}
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int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
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{
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return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
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}
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static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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/* if this is the driver that initiated the fw reset, devlink completed the reload */
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if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
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complete(&fw_reset->done);
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} else {
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mlx5_load_one(dev, false);
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devlink_remote_reload_actions_performed(priv_to_devlink(dev), 0,
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BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
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BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
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}
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}
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static void mlx5_sync_reset_reload_work(struct work_struct *work)
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{
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struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
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reset_reload_work);
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struct mlx5_core_dev *dev = fw_reset->dev;
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int err;
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mlx5_enter_error_state(dev, true);
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mlx5_unload_one(dev, false);
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err = mlx5_health_wait_pci_up(dev);
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if (err)
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mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
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fw_reset->ret = err;
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mlx5_fw_reset_complete_reload(dev);
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}
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static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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del_timer_sync(&fw_reset->timer);
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}
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static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
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mlx5_core_warn(dev, "Reset request was already cleared\n");
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return -EALREADY;
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}
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mlx5_stop_sync_reset_poll(dev);
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if (poll_health)
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mlx5_start_health_poll(dev);
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return 0;
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}
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#define MLX5_RESET_POLL_INTERVAL (HZ / 10)
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static void poll_sync_reset(struct timer_list *t)
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{
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struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
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struct mlx5_core_dev *dev = fw_reset->dev;
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u32 fatal_error;
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if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
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return;
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fatal_error = mlx5_health_check_fatal_sensors(dev);
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if (fatal_error) {
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mlx5_core_warn(dev, "Got Device Reset\n");
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mlx5_sync_reset_clear_reset_requested(dev, false);
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queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
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return;
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}
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mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
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}
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static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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timer_setup(&fw_reset->timer, poll_sync_reset, 0);
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fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
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add_timer(&fw_reset->timer);
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}
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static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
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{
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return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
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}
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static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
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{
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return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
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}
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static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
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mlx5_core_warn(dev, "Reset request was already set\n");
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return -EALREADY;
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}
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mlx5_stop_health_poll(dev, true);
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mlx5_start_sync_reset_poll(dev);
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return 0;
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}
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static void mlx5_fw_live_patch_event(struct work_struct *work)
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{
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struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
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fw_live_patch_work);
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struct mlx5_core_dev *dev = fw_reset->dev;
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struct mlx5_fw_tracer *tracer;
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mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
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fw_rev_min(dev), fw_rev_sub(dev));
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tracer = dev->tracer;
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if (IS_ERR_OR_NULL(tracer))
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return;
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if (mlx5_fw_tracer_reload(tracer))
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mlx5_core_err(dev, "Failed to reload FW tracer\n");
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}
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static void mlx5_sync_reset_request_event(struct work_struct *work)
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{
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struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
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reset_request_work);
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struct mlx5_core_dev *dev = fw_reset->dev;
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int err;
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if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags)) {
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err = mlx5_fw_reset_set_reset_sync_nack(dev);
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mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
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err ? "Failed" : "Sent");
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return;
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}
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if (mlx5_sync_reset_set_reset_requested(dev))
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return;
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err = mlx5_fw_reset_set_reset_sync_ack(dev);
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if (err)
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mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
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else
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mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
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}
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#define MLX5_PCI_LINK_UP_TIMEOUT 2000
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static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
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{
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struct pci_bus *bridge_bus = dev->pdev->bus;
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struct pci_dev *bridge = bridge_bus->self;
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u16 reg16, dev_id, sdev_id;
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unsigned long timeout;
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struct pci_dev *sdev;
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int cap, err;
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u32 reg32;
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/* Check that all functions under the pci bridge are PFs of
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* this device otherwise fail this function.
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*/
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err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
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if (err)
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return err;
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list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
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err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
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if (err)
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return err;
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if (sdev_id != dev_id)
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return -EPERM;
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}
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cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
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if (!cap)
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return -EOPNOTSUPP;
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list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
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pci_save_state(sdev);
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pci_cfg_access_lock(sdev);
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}
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/* PCI link toggle */
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err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
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if (err)
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return err;
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msleep(500);
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err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
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if (err)
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return err;
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/* Check link */
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err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, ®32);
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if (err)
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return err;
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if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
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mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32);
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msleep(1000);
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goto restore;
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}
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timeout = jiffies + msecs_to_jiffies(MLX5_PCI_LINK_UP_TIMEOUT);
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do {
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err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16);
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if (err)
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return err;
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if (reg16 & PCI_EXP_LNKSTA_DLLLA)
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break;
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msleep(20);
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} while (!time_after(jiffies, timeout));
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if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
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mlx5_core_info(dev, "PCI Link up\n");
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} else {
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mlx5_core_err(dev, "PCI link not ready (0x%04x) after %d ms\n",
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reg16, MLX5_PCI_LINK_UP_TIMEOUT);
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err = -ETIMEDOUT;
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}
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restore:
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list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
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pci_cfg_access_unlock(sdev);
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pci_restore_state(sdev);
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}
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return err;
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}
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static void mlx5_sync_reset_now_event(struct work_struct *work)
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{
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struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
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reset_now_work);
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struct mlx5_core_dev *dev = fw_reset->dev;
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int err;
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if (mlx5_sync_reset_clear_reset_requested(dev, false))
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return;
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mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
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err = mlx5_cmd_fast_teardown_hca(dev);
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if (err) {
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mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
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goto done;
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}
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err = mlx5_pci_link_toggle(dev);
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if (err) {
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mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
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goto done;
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}
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mlx5_enter_error_state(dev, true);
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mlx5_unload_one(dev, false);
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done:
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fw_reset->ret = err;
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mlx5_fw_reset_complete_reload(dev);
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}
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static void mlx5_sync_reset_abort_event(struct work_struct *work)
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{
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struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
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reset_abort_work);
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struct mlx5_core_dev *dev = fw_reset->dev;
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if (mlx5_sync_reset_clear_reset_requested(dev, true))
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return;
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mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
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}
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static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
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{
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struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
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u8 sync_event_rst_type;
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sync_fw_update_eqe = &eqe->data.sync_fw_update;
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sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
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switch (sync_event_rst_type) {
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case MLX5_SYNC_RST_STATE_RESET_REQUEST:
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queue_work(fw_reset->wq, &fw_reset->reset_request_work);
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break;
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case MLX5_SYNC_RST_STATE_RESET_NOW:
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queue_work(fw_reset->wq, &fw_reset->reset_now_work);
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break;
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case MLX5_SYNC_RST_STATE_RESET_ABORT:
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queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
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break;
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}
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}
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static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
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{
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struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
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struct mlx5_eqe *eqe = data;
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switch (eqe->sub_type) {
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case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
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queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
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break;
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case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
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mlx5_sync_reset_events_handle(fw_reset, eqe);
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break;
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default:
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return NOTIFY_DONE;
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}
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return NOTIFY_OK;
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}
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#define MLX5_FW_RESET_TIMEOUT_MSEC 5000
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int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
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{
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unsigned long timeout = msecs_to_jiffies(MLX5_FW_RESET_TIMEOUT_MSEC);
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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int err;
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if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
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mlx5_core_warn(dev, "FW sync reset timeout after %d seconds\n",
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MLX5_FW_RESET_TIMEOUT_MSEC / 1000);
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err = -ETIMEDOUT;
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goto out;
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}
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err = fw_reset->ret;
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out:
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clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
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return err;
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}
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void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
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mlx5_eq_notifier_register(dev, &fw_reset->nb);
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}
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void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
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{
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mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
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}
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int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
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if (!fw_reset)
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return -ENOMEM;
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fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
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if (!fw_reset->wq) {
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kfree(fw_reset);
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return -ENOMEM;
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}
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fw_reset->dev = dev;
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dev->priv.fw_reset = fw_reset;
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INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
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INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
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INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
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INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
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INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
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init_completion(&fw_reset->done);
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return 0;
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}
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void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
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{
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struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
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destroy_workqueue(fw_reset->wq);
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kfree(dev->priv.fw_reset);
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}
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