/*
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* Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/mlx5/device.h>
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#include "fpga/core.h"
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#include "fpga/conn.h"
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#include "fpga/sdk.h"
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struct mlx5_fpga_conn *
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mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
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struct mlx5_fpga_conn_attr *attr)
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{
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return mlx5_fpga_conn_create(fdev, attr, MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP);
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}
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EXPORT_SYMBOL(mlx5_fpga_sbu_conn_create);
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void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn)
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{
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mlx5_fpga_conn_destroy(conn);
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}
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EXPORT_SYMBOL(mlx5_fpga_sbu_conn_destroy);
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int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
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struct mlx5_fpga_dma_buf *buf)
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{
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return mlx5_fpga_conn_send(conn, buf);
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}
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EXPORT_SYMBOL(mlx5_fpga_sbu_conn_sendmsg);
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static int mlx5_fpga_mem_read_i2c(struct mlx5_fpga_device *fdev, size_t size,
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u64 addr, u8 *buf)
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{
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size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
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size_t bytes_done = 0;
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u8 actual_size;
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int err;
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if (!size)
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return -EINVAL;
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if (!fdev->mdev)
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return -ENOTCONN;
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while (bytes_done < size) {
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actual_size = min(max_size, (size - bytes_done));
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err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
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addr + bytes_done,
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buf + bytes_done, false);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to read over I2C: %d\n",
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err);
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break;
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}
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bytes_done += actual_size;
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}
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return err;
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}
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static int mlx5_fpga_mem_write_i2c(struct mlx5_fpga_device *fdev, size_t size,
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u64 addr, u8 *buf)
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{
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size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
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size_t bytes_done = 0;
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u8 actual_size;
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int err;
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if (!size)
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return -EINVAL;
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if (!fdev->mdev)
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return -ENOTCONN;
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while (bytes_done < size) {
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actual_size = min(max_size, (size - bytes_done));
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err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
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addr + bytes_done,
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buf + bytes_done, true);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to write FPGA crspace\n");
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break;
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}
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bytes_done += actual_size;
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}
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return err;
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}
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int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
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void *buf, enum mlx5_fpga_access_type access_type)
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{
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int ret;
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switch (access_type) {
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case MLX5_FPGA_ACCESS_TYPE_I2C:
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ret = mlx5_fpga_mem_read_i2c(fdev, size, addr, buf);
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if (ret)
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return ret;
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break;
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default:
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mlx5_fpga_warn(fdev, "Unexpected read access_type %u\n",
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access_type);
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return -EACCES;
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}
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return size;
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}
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EXPORT_SYMBOL(mlx5_fpga_mem_read);
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int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
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void *buf, enum mlx5_fpga_access_type access_type)
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{
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int ret;
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switch (access_type) {
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case MLX5_FPGA_ACCESS_TYPE_I2C:
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ret = mlx5_fpga_mem_write_i2c(fdev, size, addr, buf);
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if (ret)
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return ret;
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break;
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default:
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mlx5_fpga_warn(fdev, "Unexpected write access_type %u\n",
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access_type);
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return -EACCES;
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}
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return size;
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}
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EXPORT_SYMBOL(mlx5_fpga_mem_write);
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int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf)
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{
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return mlx5_fpga_sbu_caps(fdev->mdev, buf, size);
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}
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EXPORT_SYMBOL(mlx5_fpga_get_sbu_caps);
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