/*
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* Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_FPGA_CORE_H__
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#define __MLX5_FPGA_CORE_H__
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#ifdef CONFIG_MLX5_FPGA
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#include <linux/mlx5/eq.h>
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#include "mlx5_core.h"
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#include "lib/eq.h"
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#include "fpga/cmd.h"
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/* Represents an Innova device */
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struct mlx5_fpga_device {
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struct mlx5_core_dev *mdev;
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struct mlx5_nb fpga_err_nb;
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struct mlx5_nb fpga_qp_err_nb;
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spinlock_t state_lock; /* Protects state transitions */
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enum mlx5_fpga_status state;
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enum mlx5_fpga_image last_admin_image;
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enum mlx5_fpga_image last_oper_image;
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/* QP Connection resources */
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struct {
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u32 pdn;
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struct mlx5_core_mkey mkey;
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struct mlx5_uars_page *uar;
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} conn_res;
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struct mlx5_fpga_ipsec *ipsec;
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struct mlx5_fpga_tls *tls;
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};
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#define mlx5_fpga_dbg(__adev, format, ...) \
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mlx5_core_dbg((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
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__func__, __LINE__, current->pid, ##__VA_ARGS__)
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#define mlx5_fpga_err(__adev, format, ...) \
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mlx5_core_err((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
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__func__, __LINE__, current->pid, ##__VA_ARGS__)
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#define mlx5_fpga_warn(__adev, format, ...) \
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mlx5_core_warn((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
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__func__, __LINE__, current->pid, ##__VA_ARGS__)
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#define mlx5_fpga_warn_ratelimited(__adev, format, ...) \
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mlx5_core_err_rl((__adev)->mdev, "FPGA: %s:%d: " \
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format, __func__, __LINE__, ##__VA_ARGS__)
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#define mlx5_fpga_notice(__adev, format, ...) \
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mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
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#define mlx5_fpga_info(__adev, format, ...) \
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mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
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int mlx5_fpga_init(struct mlx5_core_dev *mdev);
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void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev);
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int mlx5_fpga_device_start(struct mlx5_core_dev *mdev);
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void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev);
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#else
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static inline int mlx5_fpga_init(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
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{
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}
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static inline int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
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{
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}
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#endif
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#endif /* __MLX5_FPGA_CORE_H__ */
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