/*
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* Copyright (c) 2017, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/module.h>
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#include <linux/etherdevice.h>
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#include <linux/mlx5/driver.h>
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#include "mlx5_core.h"
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#include "lib/mlx5.h"
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#include "lib/eq.h"
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#include "fpga/core.h"
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#include "fpga/conn.h"
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static const char *const mlx5_fpga_error_strings[] = {
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"Null Syndrome",
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"Corrupted DDR",
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"Flash Timeout",
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"Internal Link Error",
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"Watchdog HW Failure",
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"I2C Failure",
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"Image Changed",
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"Temperature Critical",
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};
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static const char * const mlx5_fpga_qp_error_strings[] = {
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"Null Syndrome",
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"Retry Counter Expired",
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"RNR Expired",
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};
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static struct mlx5_fpga_device *mlx5_fpga_device_alloc(void)
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{
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struct mlx5_fpga_device *fdev = NULL;
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fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
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if (!fdev)
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return NULL;
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spin_lock_init(&fdev->state_lock);
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fdev->state = MLX5_FPGA_STATUS_NONE;
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return fdev;
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}
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static const char *mlx5_fpga_image_name(enum mlx5_fpga_image image)
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{
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switch (image) {
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case MLX5_FPGA_IMAGE_USER:
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return "user";
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case MLX5_FPGA_IMAGE_FACTORY:
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return "factory";
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default:
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return "unknown";
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}
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}
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static const char *mlx5_fpga_name(u32 fpga_id)
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{
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static char ret[32];
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switch (fpga_id) {
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case MLX5_FPGA_NEWTON:
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return "Newton";
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case MLX5_FPGA_EDISON:
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return "Edison";
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case MLX5_FPGA_MORSE:
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return "Morse";
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case MLX5_FPGA_MORSEQ:
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return "MorseQ";
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}
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snprintf(ret, sizeof(ret), "Unknown %d", fpga_id);
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return ret;
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}
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static int mlx5_is_fpga_lookaside(u32 fpga_id)
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{
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return fpga_id != MLX5_FPGA_NEWTON && fpga_id != MLX5_FPGA_EDISON;
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}
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static int mlx5_fpga_device_load_check(struct mlx5_fpga_device *fdev)
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{
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struct mlx5_fpga_query query;
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int err;
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err = mlx5_fpga_query(fdev->mdev, &query);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to query status: %d\n", err);
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return err;
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}
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fdev->last_admin_image = query.admin_image;
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fdev->last_oper_image = query.oper_image;
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mlx5_fpga_info(fdev, "Status %u; Admin image %u; Oper image %u\n",
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query.status, query.admin_image, query.oper_image);
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/* for FPGA lookaside projects FPGA load status is not important */
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if (mlx5_is_fpga_lookaside(MLX5_CAP_FPGA(fdev->mdev, fpga_id)))
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return 0;
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if (query.status != MLX5_FPGA_STATUS_SUCCESS) {
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mlx5_fpga_err(fdev, "%s image failed to load; status %u\n",
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mlx5_fpga_image_name(fdev->last_oper_image),
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query.status);
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return -EIO;
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}
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return 0;
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}
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static int mlx5_fpga_device_brb(struct mlx5_fpga_device *fdev)
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{
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int err;
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struct mlx5_core_dev *mdev = fdev->mdev;
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err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to set bypass on: %d\n", err);
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return err;
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}
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err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to reset SBU: %d\n", err);
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return err;
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}
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err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF);
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if (err) {
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mlx5_fpga_err(fdev, "Failed to set bypass off: %d\n", err);
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return err;
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}
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return 0;
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}
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static int mlx5_fpga_event(struct mlx5_fpga_device *, unsigned long, void *);
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static int fpga_err_event(struct notifier_block *nb, unsigned long event, void *eqe)
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{
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struct mlx5_fpga_device *fdev = mlx5_nb_cof(nb, struct mlx5_fpga_device, fpga_err_nb);
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return mlx5_fpga_event(fdev, event, eqe);
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}
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static int fpga_qp_err_event(struct notifier_block *nb, unsigned long event, void *eqe)
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{
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struct mlx5_fpga_device *fdev = mlx5_nb_cof(nb, struct mlx5_fpga_device, fpga_qp_err_nb);
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return mlx5_fpga_event(fdev, event, eqe);
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}
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int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_device *fdev = mdev->fpga;
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unsigned int max_num_qps;
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unsigned long flags;
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u32 fpga_id;
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int err;
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if (!fdev)
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return 0;
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err = mlx5_fpga_caps(fdev->mdev);
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if (err)
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goto out;
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err = mlx5_fpga_device_load_check(fdev);
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if (err)
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goto out;
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fpga_id = MLX5_CAP_FPGA(fdev->mdev, fpga_id);
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mlx5_fpga_info(fdev, "FPGA card %s:%u\n", mlx5_fpga_name(fpga_id), fpga_id);
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/* No QPs if FPGA does not participate in net processing */
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if (mlx5_is_fpga_lookaside(fpga_id))
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goto out;
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mlx5_fpga_info(fdev, "%s(%d): image, version %u; SBU %06x:%04x version %d\n",
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mlx5_fpga_image_name(fdev->last_oper_image),
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fdev->last_oper_image,
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MLX5_CAP_FPGA(fdev->mdev, image_version),
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MLX5_CAP_FPGA(fdev->mdev, ieee_vendor_id),
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MLX5_CAP_FPGA(fdev->mdev, sandbox_product_id),
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MLX5_CAP_FPGA(fdev->mdev, sandbox_product_version));
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max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);
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if (!max_num_qps) {
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mlx5_fpga_err(fdev, "FPGA reports 0 QPs in SHELL_CAPS\n");
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err = -ENOTSUPP;
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goto out;
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}
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err = mlx5_core_reserve_gids(mdev, max_num_qps);
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if (err)
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goto out;
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MLX5_NB_INIT(&fdev->fpga_err_nb, fpga_err_event, FPGA_ERROR);
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MLX5_NB_INIT(&fdev->fpga_qp_err_nb, fpga_qp_err_event, FPGA_QP_ERROR);
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mlx5_eq_notifier_register(fdev->mdev, &fdev->fpga_err_nb);
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mlx5_eq_notifier_register(fdev->mdev, &fdev->fpga_qp_err_nb);
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err = mlx5_fpga_conn_device_init(fdev);
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if (err)
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goto err_rsvd_gid;
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if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
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err = mlx5_fpga_device_brb(fdev);
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if (err)
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goto err_conn_init;
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}
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goto out;
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err_conn_init:
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mlx5_fpga_conn_device_cleanup(fdev);
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err_rsvd_gid:
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mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_err_nb);
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mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_qp_err_nb);
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mlx5_core_unreserve_gids(mdev, max_num_qps);
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out:
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spin_lock_irqsave(&fdev->state_lock, flags);
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fdev->state = err ? MLX5_FPGA_STATUS_FAILURE : MLX5_FPGA_STATUS_SUCCESS;
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spin_unlock_irqrestore(&fdev->state_lock, flags);
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return err;
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}
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int mlx5_fpga_init(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_device *fdev = NULL;
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if (!MLX5_CAP_GEN(mdev, fpga)) {
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mlx5_core_dbg(mdev, "FPGA capability not present\n");
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return 0;
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}
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mlx5_core_dbg(mdev, "Initializing FPGA\n");
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fdev = mlx5_fpga_device_alloc();
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if (!fdev)
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return -ENOMEM;
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fdev->mdev = mdev;
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mdev->fpga = fdev;
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return 0;
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}
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void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_device *fdev = mdev->fpga;
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unsigned int max_num_qps;
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unsigned long flags;
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int err;
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if (!fdev)
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return;
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if (mlx5_is_fpga_lookaside(MLX5_CAP_FPGA(fdev->mdev, fpga_id)))
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return;
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spin_lock_irqsave(&fdev->state_lock, flags);
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if (fdev->state != MLX5_FPGA_STATUS_SUCCESS) {
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spin_unlock_irqrestore(&fdev->state_lock, flags);
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return;
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}
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fdev->state = MLX5_FPGA_STATUS_NONE;
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spin_unlock_irqrestore(&fdev->state_lock, flags);
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if (fdev->last_oper_image == MLX5_FPGA_IMAGE_USER) {
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err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON);
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if (err)
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mlx5_fpga_err(fdev, "Failed to re-set SBU bypass on: %d\n",
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err);
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}
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mlx5_fpga_conn_device_cleanup(fdev);
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mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_err_nb);
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mlx5_eq_notifier_unregister(fdev->mdev, &fdev->fpga_qp_err_nb);
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max_num_qps = MLX5_CAP_FPGA(mdev, shell_caps.max_num_qps);
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mlx5_core_unreserve_gids(mdev, max_num_qps);
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}
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void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
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{
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struct mlx5_fpga_device *fdev = mdev->fpga;
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mlx5_fpga_device_stop(mdev);
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kfree(fdev);
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mdev->fpga = NULL;
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}
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static const char *mlx5_fpga_syndrome_to_string(u8 syndrome)
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{
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if (syndrome < ARRAY_SIZE(mlx5_fpga_error_strings))
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return mlx5_fpga_error_strings[syndrome];
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return "Unknown";
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}
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static const char *mlx5_fpga_qp_syndrome_to_string(u8 syndrome)
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{
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if (syndrome < ARRAY_SIZE(mlx5_fpga_qp_error_strings))
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return mlx5_fpga_qp_error_strings[syndrome];
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return "Unknown";
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}
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static int mlx5_fpga_event(struct mlx5_fpga_device *fdev,
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unsigned long event, void *eqe)
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{
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void *data = ((struct mlx5_eqe *)eqe)->data.raw;
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const char *event_name;
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bool teardown = false;
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unsigned long flags;
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u8 syndrome;
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switch (event) {
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case MLX5_EVENT_TYPE_FPGA_ERROR:
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syndrome = MLX5_GET(fpga_error_event, data, syndrome);
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event_name = mlx5_fpga_syndrome_to_string(syndrome);
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break;
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case MLX5_EVENT_TYPE_FPGA_QP_ERROR:
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syndrome = MLX5_GET(fpga_qp_error_event, data, syndrome);
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event_name = mlx5_fpga_qp_syndrome_to_string(syndrome);
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break;
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default:
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return NOTIFY_DONE;
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}
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spin_lock_irqsave(&fdev->state_lock, flags);
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switch (fdev->state) {
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case MLX5_FPGA_STATUS_SUCCESS:
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mlx5_fpga_warn(fdev, "Error %u: %s\n", syndrome, event_name);
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teardown = true;
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break;
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default:
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mlx5_fpga_warn_ratelimited(fdev, "Unexpected error event %u: %s\n",
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syndrome, event_name);
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}
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spin_unlock_irqrestore(&fdev->state_lock, flags);
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/* We tear-down the card's interfaces and functionality because
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* the FPGA bump-on-the-wire is misbehaving and we lose ability
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* to communicate with the network. User may still be able to
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* recover by re-programming or debugging the FPGA
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*/
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if (teardown)
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mlx5_trigger_health_work(fdev->mdev);
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return NOTIFY_OK;
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}
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