/*
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* Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_FPGA_H__
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#define __MLX5_FPGA_H__
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#include <linux/mlx5/driver.h>
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enum mlx5_fpga_id {
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MLX5_FPGA_NEWTON = 0,
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MLX5_FPGA_EDISON = 1,
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MLX5_FPGA_MORSE = 2,
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MLX5_FPGA_MORSEQ = 3,
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};
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enum mlx5_fpga_image {
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MLX5_FPGA_IMAGE_USER = 0,
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MLX5_FPGA_IMAGE_FACTORY,
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};
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enum mlx5_fpga_status {
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MLX5_FPGA_STATUS_SUCCESS = 0,
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MLX5_FPGA_STATUS_FAILURE = 1,
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MLX5_FPGA_STATUS_IN_PROGRESS = 2,
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MLX5_FPGA_STATUS_NONE = 0xFFFF,
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};
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struct mlx5_fpga_query {
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enum mlx5_fpga_image admin_image;
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enum mlx5_fpga_image oper_image;
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enum mlx5_fpga_status status;
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};
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enum mlx5_fpga_qpc_field_select {
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MLX5_FPGA_QPC_STATE = BIT(0),
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};
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struct mlx5_fpga_qp_counters {
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u64 rx_ack_packets;
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u64 rx_send_packets;
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u64 tx_ack_packets;
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u64 tx_send_packets;
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u64 rx_total_drop;
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};
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int mlx5_fpga_caps(struct mlx5_core_dev *dev);
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int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
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int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
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int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
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void *buf, bool write);
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int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size);
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int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
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u32 *fpga_qpn);
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int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
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enum mlx5_fpga_qpc_field_select fields, void *fpga_qpc);
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int mlx5_fpga_query_qp(struct mlx5_core_dev *dev, u32 fpga_qpn, void *fpga_qpc);
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int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
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bool clear, struct mlx5_fpga_qp_counters *data);
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int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn);
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#endif /* __MLX5_FPGA_H__ */
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