/*
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* Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_ESWITCH_H__
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#define __MLX5_ESWITCH_H__
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#include <linux/if_ether.h>
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#include <linux/if_link.h>
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#include <linux/atomic.h>
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#include <net/devlink.h>
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#include <linux/mlx5/device.h>
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#include <linux/mlx5/eswitch.h>
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#include <linux/mlx5/vport.h>
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#include <linux/mlx5/fs.h>
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#include "lib/mpfs.h"
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#include "lib/fs_chains.h"
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#include "en/tc_ct.h"
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#ifdef CONFIG_MLX5_ESWITCH
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#define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15
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#define MLX5_MAX_UC_PER_VPORT(dev) \
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(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
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#define MLX5_MAX_MC_PER_VPORT(dev) \
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(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
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#define MLX5_MIN_BW_SHARE 1
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#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
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min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
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#define mlx5_esw_has_fwd_fdb(dev) \
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MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
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#define esw_chains(esw) \
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((esw)->fdb_table.offloads.esw_chains_priv)
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struct vport_ingress {
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struct mlx5_flow_table *acl;
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struct mlx5_flow_handle *allow_rule;
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struct {
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struct mlx5_flow_group *allow_spoofchk_only_grp;
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struct mlx5_flow_group *allow_untagged_spoofchk_grp;
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struct mlx5_flow_group *allow_untagged_only_grp;
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struct mlx5_flow_group *drop_grp;
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struct mlx5_flow_handle *drop_rule;
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struct mlx5_fc *drop_counter;
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} legacy;
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struct {
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/* Optional group to add an FTE to do internal priority
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* tagging on ingress packets.
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*/
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struct mlx5_flow_group *metadata_prio_tag_grp;
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/* Group to add default match-all FTE entry to tag ingress
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* packet with metadata.
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*/
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struct mlx5_flow_group *metadata_allmatch_grp;
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struct mlx5_modify_hdr *modify_metadata;
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struct mlx5_flow_handle *modify_metadata_rule;
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} offloads;
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};
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struct vport_egress {
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struct mlx5_flow_table *acl;
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struct mlx5_flow_handle *allowed_vlan;
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struct mlx5_flow_group *vlan_grp;
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union {
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struct {
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struct mlx5_flow_group *drop_grp;
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struct mlx5_flow_handle *drop_rule;
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struct mlx5_fc *drop_counter;
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} legacy;
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struct {
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struct mlx5_flow_group *fwd_grp;
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struct mlx5_flow_handle *fwd_rule;
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} offloads;
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};
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};
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struct mlx5_vport_drop_stats {
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u64 rx_dropped;
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u64 tx_dropped;
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};
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struct mlx5_vport_info {
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u8 mac[ETH_ALEN];
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u16 vlan;
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u8 qos;
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u64 node_guid;
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int link_state;
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u32 min_rate;
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u32 max_rate;
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bool spoofchk;
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bool trusted;
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};
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/* Vport context events */
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enum mlx5_eswitch_vport_event {
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MLX5_VPORT_UC_ADDR_CHANGE = BIT(0),
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MLX5_VPORT_MC_ADDR_CHANGE = BIT(1),
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MLX5_VPORT_PROMISC_CHANGE = BIT(3),
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};
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struct mlx5_vport {
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struct mlx5_core_dev *dev;
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int vport;
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struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
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struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
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struct mlx5_flow_handle *promisc_rule;
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struct mlx5_flow_handle *allmulti_rule;
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struct work_struct vport_change_handler;
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struct vport_ingress ingress;
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struct vport_egress egress;
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u32 default_metadata;
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u32 metadata;
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struct mlx5_vport_info info;
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struct {
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bool enabled;
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u32 esw_tsar_ix;
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u32 bw_share;
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} qos;
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bool enabled;
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enum mlx5_eswitch_vport_event enabled_events;
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struct devlink_port *dl_port;
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};
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struct mlx5_eswitch_fdb {
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union {
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struct legacy_fdb {
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struct mlx5_flow_table *fdb;
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struct mlx5_flow_group *addr_grp;
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struct mlx5_flow_group *allmulti_grp;
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struct mlx5_flow_group *promisc_grp;
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struct mlx5_flow_table *vepa_fdb;
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struct mlx5_flow_handle *vepa_uplink_rule;
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struct mlx5_flow_handle *vepa_star_rule;
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} legacy;
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struct offloads_fdb {
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struct mlx5_flow_namespace *ns;
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struct mlx5_flow_table *slow_fdb;
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struct mlx5_flow_group *send_to_vport_grp;
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struct mlx5_flow_group *peer_miss_grp;
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struct mlx5_flow_handle **peer_miss_rules;
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struct mlx5_flow_group *miss_grp;
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struct mlx5_flow_handle *miss_rule_uni;
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struct mlx5_flow_handle *miss_rule_multi;
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int vlan_push_pop_refcount;
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struct mlx5_fs_chains *esw_chains_priv;
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struct {
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DECLARE_HASHTABLE(table, 8);
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/* Protects vports.table */
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struct mutex lock;
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} vports;
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} offloads;
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};
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u32 flags;
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};
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struct mlx5_esw_offload {
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struct mlx5_flow_table *ft_offloads_restore;
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struct mlx5_flow_group *restore_group;
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struct mlx5_modify_hdr *restore_copy_hdr_id;
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struct mlx5_flow_table *ft_offloads;
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struct mlx5_flow_group *vport_rx_group;
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struct mlx5_eswitch_rep *vport_reps;
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struct list_head peer_flows;
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struct mutex peer_mutex;
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struct mutex encap_tbl_lock; /* protects encap_tbl */
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DECLARE_HASHTABLE(encap_tbl, 8);
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struct mutex decap_tbl_lock; /* protects decap_tbl */
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DECLARE_HASHTABLE(decap_tbl, 8);
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struct mod_hdr_tbl mod_hdr;
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DECLARE_HASHTABLE(termtbl_tbl, 8);
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struct mutex termtbl_mutex; /* protects termtbl hash */
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const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES];
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u8 inline_mode;
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atomic64_t num_flows;
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enum devlink_eswitch_encap_mode encap;
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struct ida vport_metadata_ida;
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unsigned int host_number; /* ECPF supports one external host */
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};
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/* E-Switch MC FDB table hash node */
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struct esw_mc_addr { /* SRIOV only */
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struct l2addr_node node;
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struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
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u32 refcnt;
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};
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struct mlx5_host_work {
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struct work_struct work;
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struct mlx5_eswitch *esw;
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};
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struct mlx5_esw_functions {
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struct mlx5_nb nb;
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u16 num_vfs;
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};
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enum {
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MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0),
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MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1),
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};
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struct mlx5_eswitch {
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struct mlx5_core_dev *dev;
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struct mlx5_nb nb;
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struct mlx5_eswitch_fdb fdb_table;
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/* legacy data structures */
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struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
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struct esw_mc_addr mc_promisc;
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/* end of legacy */
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struct workqueue_struct *work_queue;
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struct mlx5_vport *vports;
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u32 flags;
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int total_vports;
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int enabled_vports;
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/* Synchronize between vport change events
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* and async SRIOV admin state changes
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*/
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struct mutex state_lock;
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/* Protects eswitch mode change that occurs via one or more
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* user commands, i.e. sriov state change, devlink commands.
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*/
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struct rw_semaphore mode_lock;
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struct {
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bool enabled;
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u32 root_tsar_id;
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} qos;
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struct mlx5_esw_offload offloads;
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int mode;
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u16 manager_vport;
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u16 first_host_vport;
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struct mlx5_esw_functions esw_funcs;
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struct {
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u32 large_group_num;
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} params;
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};
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void esw_offloads_disable(struct mlx5_eswitch *esw);
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int esw_offloads_enable(struct mlx5_eswitch *esw);
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void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
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int esw_offloads_init_reps(struct mlx5_eswitch *esw);
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u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw);
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void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata);
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int mlx5_esw_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num,
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u32 rate_mbps);
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/* E-Switch API */
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int mlx5_eswitch_init(struct mlx5_core_dev *dev);
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void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
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#define MLX5_ESWITCH_IGNORE_NUM_VFS (-1)
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int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs);
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int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs);
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void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw, bool clear_vf);
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void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf);
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int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
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u16 vport, const u8 *mac);
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int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
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u16 vport, int link_state);
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int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
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u16 vport, u16 vlan, u8 qos);
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int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
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u16 vport, bool spoofchk);
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int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
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u16 vport_num, bool setting);
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int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
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u32 max_rate, u32 min_rate);
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int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
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int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
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int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
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u16 vport, struct ifla_vf_info *ivi);
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int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
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u16 vport,
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struct ifla_vf_stats *vf_stats);
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void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
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int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport,
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bool other_vport, void *in);
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struct mlx5_flow_spec;
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struct mlx5_esw_flow_attr;
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struct mlx5_termtbl_handle;
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bool
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mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw,
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struct mlx5_flow_attr *attr,
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struct mlx5_flow_act *flow_act,
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struct mlx5_flow_spec *spec);
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struct mlx5_flow_handle *
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mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw,
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struct mlx5_flow_table *ft,
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struct mlx5_flow_spec *spec,
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struct mlx5_esw_flow_attr *attr,
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struct mlx5_flow_act *flow_act,
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struct mlx5_flow_destination *dest,
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int num_dest);
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void
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mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw,
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struct mlx5_termtbl_handle *tt);
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struct mlx5_flow_handle *
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mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
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struct mlx5_flow_spec *spec,
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struct mlx5_flow_attr *attr);
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struct mlx5_flow_handle *
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mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
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struct mlx5_flow_spec *spec,
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struct mlx5_flow_attr *attr);
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void
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mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
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struct mlx5_flow_handle *rule,
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struct mlx5_flow_attr *attr);
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void
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mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
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struct mlx5_flow_handle *rule,
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struct mlx5_flow_attr *attr);
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struct mlx5_flow_handle *
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mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
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struct mlx5_flow_destination *dest);
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enum {
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SET_VLAN_STRIP = BIT(0),
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SET_VLAN_INSERT = BIT(1)
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};
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enum mlx5_flow_match_level {
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MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
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MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
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MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
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MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
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};
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/* current maximum for flow based vport multicasting */
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#define MLX5_MAX_FLOW_FWD_VPORTS 2
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enum {
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MLX5_ESW_DEST_ENCAP = BIT(0),
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MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
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};
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enum {
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MLX5_ESW_ATTR_FLAG_VLAN_HANDLED = BIT(0),
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MLX5_ESW_ATTR_FLAG_SLOW_PATH = BIT(1),
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MLX5_ESW_ATTR_FLAG_NO_IN_PORT = BIT(2),
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};
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struct mlx5_esw_flow_attr {
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struct mlx5_eswitch_rep *in_rep;
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struct mlx5_core_dev *in_mdev;
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struct mlx5_core_dev *counter_dev;
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int split_count;
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int out_count;
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__be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
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u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
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u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
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u8 total_vlan;
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struct {
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u32 flags;
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struct mlx5_eswitch_rep *rep;
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struct mlx5_pkt_reformat *pkt_reformat;
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struct mlx5_core_dev *mdev;
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struct mlx5_termtbl_handle *termtbl;
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} dests[MLX5_MAX_FLOW_FWD_VPORTS];
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struct mlx5_pkt_reformat *decap_pkt_reformat;
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};
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int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
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struct netlink_ext_ack *extack);
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int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
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int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
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struct netlink_ext_ack *extack);
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int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
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int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
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enum devlink_eswitch_encap_mode encap,
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struct netlink_ext_ack *extack);
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int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
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enum devlink_eswitch_encap_mode *encap);
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int mlx5_devlink_port_function_hw_addr_get(struct devlink *devlink,
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struct devlink_port *port,
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u8 *hw_addr, int *hw_addr_len,
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struct netlink_ext_ack *extack);
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int mlx5_devlink_port_function_hw_addr_set(struct devlink *devlink,
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struct devlink_port *port,
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const u8 *hw_addr, int hw_addr_len,
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struct netlink_ext_ack *extack);
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void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
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int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
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struct mlx5_flow_attr *attr);
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int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
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struct mlx5_flow_attr *attr);
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int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
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u16 vport, u16 vlan, u8 qos, u8 set_flags);
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static inline bool mlx5_esw_qos_enabled(struct mlx5_eswitch *esw)
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{
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return esw->qos.enabled;
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}
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static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
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u8 vlan_depth)
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{
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bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
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MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
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if (vlan_depth == 1)
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return ret;
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return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
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MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
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}
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bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
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struct mlx5_core_dev *dev1);
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bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
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struct mlx5_core_dev *dev1);
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const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev);
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#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
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#define esw_info(__dev, format, ...) \
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dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
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#define esw_warn(__dev, format, ...) \
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dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
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#define esw_debug(dev, format, ...) \
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mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
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/* The returned number is valid only when the dev is eswitch manager. */
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static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
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{
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return mlx5_core_is_ecpf_esw_manager(dev) ?
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MLX5_VPORT_ECPF : MLX5_VPORT_PF;
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}
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static inline bool
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mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num)
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{
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return esw->manager_vport == vport_num;
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}
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static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev)
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{
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return mlx5_core_is_ecpf_esw_manager(dev) ?
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MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF;
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}
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static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev)
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{
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return mlx5_core_is_ecpf_esw_manager(dev);
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}
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static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
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{
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/* Uplink always locate at the last element of the array.*/
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return esw->total_vports - 1;
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}
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static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
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{
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return esw->total_vports - 2;
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}
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static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
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u16 vport_num)
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{
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if (vport_num == MLX5_VPORT_ECPF) {
|
if (!mlx5_ecpf_vport_exists(esw->dev))
|
esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
|
return mlx5_eswitch_ecpf_idx(esw);
|
}
|
|
if (vport_num == MLX5_VPORT_UPLINK)
|
return mlx5_eswitch_uplink_idx(esw);
|
|
return vport_num;
|
}
|
|
static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
|
int index)
|
{
|
if (index == mlx5_eswitch_ecpf_idx(esw) &&
|
mlx5_ecpf_vport_exists(esw->dev))
|
return MLX5_VPORT_ECPF;
|
|
if (index == mlx5_eswitch_uplink_idx(esw))
|
return MLX5_VPORT_UPLINK;
|
|
return index;
|
}
|
|
static inline unsigned int
|
mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev,
|
u16 vport_num)
|
{
|
return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num;
|
}
|
|
static inline u16
|
mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index)
|
{
|
return dl_port_index & 0xffff;
|
}
|
|
/* TODO: This mlx5e_tc function shouldn't be called by eswitch */
|
void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
|
|
/* The vport getter/iterator are only valid after esw->total_vports
|
* and vport->vport are initialized in mlx5_eswitch_init.
|
*/
|
#define mlx5_esw_for_all_vports(esw, i, vport) \
|
for ((i) = MLX5_VPORT_PF; \
|
(vport) = &(esw)->vports[i], \
|
(i) < (esw)->total_vports; (i)++)
|
|
#define mlx5_esw_for_all_vports_reverse(esw, i, vport) \
|
for ((i) = (esw)->total_vports - 1; \
|
(vport) = &(esw)->vports[i], \
|
(i) >= MLX5_VPORT_PF; (i)--)
|
|
#define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
|
for ((i) = MLX5_VPORT_FIRST_VF; \
|
(vport) = &(esw)->vports[(i)], \
|
(i) <= (nvfs); (i)++)
|
|
#define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
|
for ((i) = (nvfs); \
|
(vport) = &(esw)->vports[(i)], \
|
(i) >= MLX5_VPORT_FIRST_VF; (i)--)
|
|
/* The rep getter/iterator are only valid after esw->total_vports
|
* and vport->vport are initialized in mlx5_eswitch_init.
|
*/
|
#define mlx5_esw_for_all_reps(esw, i, rep) \
|
for ((i) = MLX5_VPORT_PF; \
|
(rep) = &(esw)->offloads.vport_reps[i], \
|
(i) < (esw)->total_vports; (i)++)
|
|
#define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
|
for ((i) = MLX5_VPORT_FIRST_VF; \
|
(rep) = &(esw)->offloads.vport_reps[i], \
|
(i) <= (nvfs); (i)++)
|
|
#define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
|
for ((i) = (nvfs); \
|
(rep) = &(esw)->offloads.vport_reps[i], \
|
(i) >= MLX5_VPORT_FIRST_VF; (i)--)
|
|
#define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
|
for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
|
|
#define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
|
for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
|
|
/* Includes host PF (vport 0) if it's not esw manager. */
|
#define mlx5_esw_for_each_host_func_rep(esw, i, rep, nvfs) \
|
for ((i) = (esw)->first_host_vport; \
|
(rep) = &(esw)->offloads.vport_reps[i], \
|
(i) <= (nvfs); (i)++)
|
|
#define mlx5_esw_for_each_host_func_rep_reverse(esw, i, rep, nvfs) \
|
for ((i) = (nvfs); \
|
(rep) = &(esw)->offloads.vport_reps[i], \
|
(i) >= (esw)->first_host_vport; (i)--)
|
|
#define mlx5_esw_for_each_host_func_vport(esw, vport, nvfs) \
|
for ((vport) = (esw)->first_host_vport; \
|
(vport) <= (nvfs); (vport)++)
|
|
#define mlx5_esw_for_each_host_func_vport_reverse(esw, vport, nvfs) \
|
for ((vport) = (nvfs); \
|
(vport) >= (esw)->first_host_vport; (vport)--)
|
|
struct mlx5_eswitch *mlx5_devlink_eswitch_get(struct devlink *devlink);
|
struct mlx5_vport *__must_check
|
mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
|
|
bool mlx5_eswitch_is_vf_vport(const struct mlx5_eswitch *esw, u16 vport_num);
|
|
int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data);
|
|
int
|
mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw,
|
enum mlx5_eswitch_vport_event enabled_events);
|
void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw);
|
|
int
|
esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
|
struct mlx5_vport *vport);
|
void
|
esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
|
struct mlx5_vport *vport);
|
|
int mlx5_esw_vport_tbl_get(struct mlx5_eswitch *esw);
|
void mlx5_esw_vport_tbl_put(struct mlx5_eswitch *esw);
|
|
struct mlx5_flow_handle *
|
esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag);
|
u32
|
esw_get_max_restore_tag(struct mlx5_eswitch *esw);
|
|
int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num);
|
void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num);
|
|
int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num,
|
enum mlx5_eswitch_vport_event enabled_events);
|
void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num);
|
|
int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs,
|
enum mlx5_eswitch_vport_event enabled_events);
|
void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs);
|
|
int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, u16 vport_num);
|
void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_eswitch *esw, u16 vport_num);
|
struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num);
|
#else /* CONFIG_MLX5_ESWITCH */
|
/* eswitch API stubs */
|
static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
|
static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
|
static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; }
|
static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw, bool clear_vf) {}
|
static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
|
static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; }
|
static inline
|
int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; }
|
static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev)
|
{
|
return ERR_PTR(-EOPNOTSUPP);
|
}
|
|
static inline struct mlx5_flow_handle *
|
esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
|
{
|
return ERR_PTR(-EOPNOTSUPP);
|
}
|
#endif /* CONFIG_MLX5_ESWITCH */
|
|
#endif /* __MLX5_ESWITCH_H__ */
|
