/*
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* Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MLX5_EN_H__
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#define __MLX5_EN_H__
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#include <linux/if_vlan.h>
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#include <linux/etherdevice.h>
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/crash_dump.h>
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/qp.h>
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#include <linux/mlx5/cq.h>
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#include <linux/mlx5/port.h>
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#include <linux/mlx5/vport.h>
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#include <linux/mlx5/transobj.h>
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#include <linux/mlx5/fs.h>
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#include <linux/rhashtable.h>
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#include <net/udp_tunnel.h>
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#include <net/switchdev.h>
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#include <net/xdp.h>
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#include <linux/dim.h>
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#include <linux/bits.h>
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#include "wq.h"
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#include "mlx5_core.h"
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#include "en_stats.h"
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#include "en/dcbnl.h"
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#include "en/fs.h"
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#include "lib/hv_vhca.h"
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extern const struct net_device_ops mlx5e_netdev_ops;
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struct page_pool;
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#define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
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#define MLX5E_METADATA_ETHER_LEN 8
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#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
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#define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
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#define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
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#define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
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#define MLX5E_MAX_NUM_TC 8
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#define MLX5_RX_HEADROOM NET_SKB_PAD
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#define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
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#define MLX5E_RX_MAX_HEAD (256)
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#define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
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(6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
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#define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
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max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
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#define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
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MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
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#define MLX5_MPWRQ_LOG_WQE_SZ 18
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#define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
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MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
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#define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
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#define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8))
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#define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2)
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#define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts)))
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/* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between
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* WQEs, This page will absorb write overflow by the hardware, when
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* receiving packets larger than MTU. These oversize packets are
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* dropped by the driver at a later stage.
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*/
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#define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1))
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#define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
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#define MLX5E_MAX_RQ_NUM_MTTS \
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(ALIGN_DOWN(U16_MAX, 4) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
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#define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
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#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
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(ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
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#define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
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(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
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(MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
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#define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
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#define MLX5E_LOG_MAX_RX_WQE_BULK \
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(ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
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#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
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#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
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#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
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#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
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#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
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#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
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MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
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#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
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#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
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#define MLX5E_DEFAULT_LRO_TIMEOUT 32
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#define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
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#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
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#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
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#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
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#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
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#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
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#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
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#define MLX5E_LOG_INDIR_RQT_SIZE 0x7
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#define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
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#define MLX5E_MIN_NUM_CHANNELS 0x1
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#define MLX5E_MAX_NUM_CHANNELS MLX5E_INDIR_RQT_SIZE
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#define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
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#define MLX5E_TX_CQ_POLL_BUDGET 128
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#define MLX5E_TX_XSK_POLL_BUDGET 64
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#define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
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#define MLX5E_UMR_WQE_INLINE_SZ \
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(sizeof(struct mlx5e_umr_wqe) + \
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ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
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MLX5_UMR_MTT_ALIGNMENT))
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#define MLX5E_UMR_WQEBBS \
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(DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
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#define MLX5E_MSG_LEVEL NETIF_MSG_LINK
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#define mlx5e_dbg(mlevel, priv, format, ...) \
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do { \
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if (NETIF_MSG_##mlevel & (priv)->msglevel) \
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netdev_warn(priv->netdev, format, \
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##__VA_ARGS__); \
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} while (0)
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enum mlx5e_rq_group {
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MLX5E_RQ_GROUP_REGULAR,
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MLX5E_RQ_GROUP_XSK,
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#define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
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};
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static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
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{
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if (mlx5_lag_is_lacp_owner(mdev))
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return 1;
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return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
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}
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static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
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{
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switch (wq_type) {
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case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
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return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
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wq_size / 2);
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default:
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return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
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wq_size / 2);
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}
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}
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/* Use this function to get max num channels (rxqs/txqs) only to create netdev */
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static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
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{
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return is_kdump_kernel() ?
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MLX5E_MIN_NUM_CHANNELS :
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min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
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}
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struct mlx5e_tx_wqe {
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struct mlx5_wqe_ctrl_seg ctrl;
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struct mlx5_wqe_eth_seg eth;
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struct mlx5_wqe_data_seg data[0];
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};
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struct mlx5e_rx_wqe_ll {
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struct mlx5_wqe_srq_next_seg next;
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struct mlx5_wqe_data_seg data[];
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};
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struct mlx5e_rx_wqe_cyc {
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struct mlx5_wqe_data_seg data[0];
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};
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struct mlx5e_umr_wqe {
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struct mlx5_wqe_ctrl_seg ctrl;
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struct mlx5_wqe_umr_ctrl_seg uctrl;
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struct mlx5_mkey_seg mkc;
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struct mlx5_mtt inline_mtts[0];
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};
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extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
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enum mlx5e_priv_flag {
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MLX5E_PFLAG_RX_CQE_BASED_MODER,
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MLX5E_PFLAG_TX_CQE_BASED_MODER,
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MLX5E_PFLAG_RX_CQE_COMPRESS,
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MLX5E_PFLAG_RX_STRIDING_RQ,
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MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
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MLX5E_PFLAG_XDP_TX_MPWQE,
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MLX5E_PFLAG_SKB_TX_MPWQE,
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MLX5E_NUM_PFLAGS, /* Keep last */
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};
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#define MLX5E_SET_PFLAG(params, pflag, enable) \
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do { \
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if (enable) \
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(params)->pflags |= BIT(pflag); \
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else \
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(params)->pflags &= ~(BIT(pflag)); \
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} while (0)
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#define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
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struct mlx5e_params {
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u8 log_sq_size;
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u8 rq_wq_type;
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u8 log_rq_mtu_frames;
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u16 num_channels;
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u8 num_tc;
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bool rx_cqe_compress_def;
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bool tunneled_offload_en;
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struct dim_cq_moder rx_cq_moderation;
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struct dim_cq_moder tx_cq_moderation;
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bool lro_en;
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u8 tx_min_inline_mode;
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bool vlan_strip_disable;
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bool scatter_fcs_en;
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bool rx_dim_enabled;
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bool tx_dim_enabled;
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u32 lro_timeout;
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u32 pflags;
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struct bpf_prog *xdp_prog;
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struct mlx5e_xsk *xsk;
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unsigned int sw_mtu;
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int hard_mtu;
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};
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enum {
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MLX5E_RQ_STATE_ENABLED,
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MLX5E_RQ_STATE_RECOVERING,
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MLX5E_RQ_STATE_AM,
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MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
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MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
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MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */
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MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */
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};
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struct mlx5e_cq {
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/* data path - accessed per cqe */
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struct mlx5_cqwq wq;
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/* data path - accessed per napi poll */
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u16 event_ctr;
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struct napi_struct *napi;
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struct mlx5_core_cq mcq;
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struct mlx5e_channel *channel;
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/* control */
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struct mlx5_core_dev *mdev;
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struct mlx5_wq_ctrl wq_ctrl;
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} ____cacheline_aligned_in_smp;
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struct mlx5e_cq_decomp {
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/* cqe decompression */
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struct mlx5_cqe64 title;
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struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
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u8 mini_arr_idx;
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u16 left;
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u16 wqe_counter;
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} ____cacheline_aligned_in_smp;
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enum mlx5e_dma_map_type {
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MLX5E_DMA_MAP_SINGLE,
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MLX5E_DMA_MAP_PAGE
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};
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struct mlx5e_sq_dma {
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dma_addr_t addr;
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u32 size;
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enum mlx5e_dma_map_type type;
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};
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enum {
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MLX5E_SQ_STATE_ENABLED,
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MLX5E_SQ_STATE_MPWQE,
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MLX5E_SQ_STATE_RECOVERING,
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MLX5E_SQ_STATE_IPSEC,
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MLX5E_SQ_STATE_AM,
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MLX5E_SQ_STATE_TLS,
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MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
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MLX5E_SQ_STATE_PENDING_XSK_TX,
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};
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struct mlx5e_tx_mpwqe {
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/* Current MPWQE session */
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struct mlx5e_tx_wqe *wqe;
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u32 bytes_count;
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u8 ds_count;
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u8 pkt_count;
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u8 inline_on;
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};
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struct mlx5e_txqsq {
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/* data path */
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/* dirtied @completion */
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u16 cc;
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u16 skb_fifo_cc;
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u32 dma_fifo_cc;
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struct dim dim; /* Adaptive Moderation */
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/* dirtied @xmit */
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u16 pc ____cacheline_aligned_in_smp;
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u16 skb_fifo_pc;
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u32 dma_fifo_pc;
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struct mlx5e_tx_mpwqe mpwqe;
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struct mlx5e_cq cq;
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/* read only */
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struct mlx5_wq_cyc wq;
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u32 dma_fifo_mask;
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u16 skb_fifo_mask;
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struct mlx5e_sq_stats *stats;
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struct {
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struct mlx5e_sq_dma *dma_fifo;
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struct sk_buff **skb_fifo;
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struct mlx5e_tx_wqe_info *wqe_info;
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} db;
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void __iomem *uar_map;
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struct netdev_queue *txq;
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u32 sqn;
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u16 stop_room;
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u8 min_inline_mode;
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struct device *pdev;
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__be32 mkey_be;
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unsigned long state;
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unsigned int hw_mtu;
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struct hwtstamp_config *tstamp;
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struct mlx5_clock *clock;
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/* control path */
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5e_channel *channel;
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int ch_ix;
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int txq_ix;
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u32 rate_limit;
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struct work_struct recover_work;
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} ____cacheline_aligned_in_smp;
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struct mlx5e_dma_info {
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dma_addr_t addr;
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union {
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struct page *page;
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struct xdp_buff *xsk;
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};
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};
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/* XDP packets can be transmitted in different ways. On completion, we need to
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* distinguish between them to clean up things in a proper way.
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*/
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enum mlx5e_xdp_xmit_mode {
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/* An xdp_frame was transmitted due to either XDP_REDIRECT from another
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* device or XDP_TX from an XSK RQ. The frame has to be unmapped and
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* returned.
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*/
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MLX5E_XDP_XMIT_MODE_FRAME,
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/* The xdp_frame was created in place as a result of XDP_TX from a
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* regular RQ. No DMA remapping happened, and the page belongs to us.
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*/
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MLX5E_XDP_XMIT_MODE_PAGE,
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/* No xdp_frame was created at all, the transmit happened from a UMEM
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* page. The UMEM Completion Ring producer pointer has to be increased.
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*/
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MLX5E_XDP_XMIT_MODE_XSK,
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};
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struct mlx5e_xdp_info {
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enum mlx5e_xdp_xmit_mode mode;
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union {
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struct {
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struct xdp_frame *xdpf;
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dma_addr_t dma_addr;
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} frame;
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struct {
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struct mlx5e_rq *rq;
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struct mlx5e_dma_info di;
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} page;
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};
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};
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struct mlx5e_xmit_data {
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dma_addr_t dma_addr;
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void *data;
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u32 len;
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};
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struct mlx5e_xdp_info_fifo {
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struct mlx5e_xdp_info *xi;
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u32 *cc;
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u32 *pc;
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u32 mask;
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};
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struct mlx5e_xdpsq;
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typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
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typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
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struct mlx5e_xmit_data *,
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struct mlx5e_xdp_info *,
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int);
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struct mlx5e_xdpsq {
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/* data path */
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/* dirtied @completion */
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u32 xdpi_fifo_cc;
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u16 cc;
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/* dirtied @xmit */
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u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
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u16 pc;
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struct mlx5_wqe_ctrl_seg *doorbell_cseg;
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struct mlx5e_tx_mpwqe mpwqe;
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struct mlx5e_cq cq;
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/* read only */
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struct xsk_buff_pool *xsk_pool;
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struct mlx5_wq_cyc wq;
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struct mlx5e_xdpsq_stats *stats;
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mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
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mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
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struct {
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struct mlx5e_xdp_wqe_info *wqe_info;
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struct mlx5e_xdp_info_fifo xdpi_fifo;
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} db;
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void __iomem *uar_map;
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u32 sqn;
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struct device *pdev;
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__be32 mkey_be;
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u8 min_inline_mode;
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unsigned long state;
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unsigned int hw_mtu;
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/* control path */
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5e_channel *channel;
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} ____cacheline_aligned_in_smp;
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struct mlx5e_icosq {
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/* data path */
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u16 cc;
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u16 pc;
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struct mlx5_wqe_ctrl_seg *doorbell_cseg;
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struct mlx5e_cq cq;
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/* write@xmit, read@completion */
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struct {
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struct mlx5e_icosq_wqe_info *wqe_info;
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} db;
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/* read only */
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struct mlx5_wq_cyc wq;
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void __iomem *uar_map;
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u32 sqn;
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unsigned long state;
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/* control path */
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5e_channel *channel;
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struct work_struct recover_work;
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} ____cacheline_aligned_in_smp;
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struct mlx5e_wqe_frag_info {
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struct mlx5e_dma_info *di;
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u32 offset;
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bool last_in_page;
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};
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struct mlx5e_umr_dma_info {
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struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
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};
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struct mlx5e_mpw_info {
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struct mlx5e_umr_dma_info umr;
|
u16 consumed_strides;
|
DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
|
};
|
|
#define MLX5E_MAX_RX_FRAGS 4
|
|
/* a single cache unit is capable to serve one napi call (for non-striding rq)
|
* or a MPWQE (for striding rq).
|
*/
|
#define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
|
MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
|
#define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
|
struct mlx5e_page_cache {
|
u32 head;
|
u32 tail;
|
struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
|
};
|
|
struct mlx5e_rq;
|
typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
|
typedef struct sk_buff *
|
(*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
|
u16 cqe_bcnt, u32 head_offset, u32 page_idx);
|
typedef struct sk_buff *
|
(*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
|
struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
|
typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
|
typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
|
|
int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk);
|
|
enum mlx5e_rq_flag {
|
MLX5E_RQ_FLAG_XDP_XMIT,
|
MLX5E_RQ_FLAG_XDP_REDIRECT,
|
};
|
|
struct mlx5e_rq_frag_info {
|
int frag_size;
|
int frag_stride;
|
};
|
|
struct mlx5e_rq_frags_info {
|
struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
|
u8 num_frags;
|
u8 log_num_frags;
|
u8 wqe_bulk;
|
};
|
|
struct mlx5e_rq {
|
/* data path */
|
union {
|
struct {
|
struct mlx5_wq_cyc wq;
|
struct mlx5e_wqe_frag_info *frags;
|
struct mlx5e_dma_info *di;
|
struct mlx5e_rq_frags_info info;
|
mlx5e_fp_skb_from_cqe skb_from_cqe;
|
} wqe;
|
struct {
|
struct mlx5_wq_ll wq;
|
struct mlx5e_umr_wqe umr_wqe;
|
struct mlx5e_mpw_info *info;
|
mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
|
u16 num_strides;
|
u16 actual_wq_head;
|
u8 log_stride_sz;
|
u8 umr_in_progress;
|
u8 umr_last_bulk;
|
u8 umr_completed;
|
} mpwqe;
|
};
|
struct {
|
u16 headroom;
|
u32 frame0_sz;
|
u8 map_dir; /* dma map direction */
|
} buff;
|
|
struct mlx5e_channel *channel;
|
struct device *pdev;
|
struct net_device *netdev;
|
struct mlx5e_rq_stats *stats;
|
struct mlx5e_cq cq;
|
struct mlx5e_cq_decomp cqd;
|
struct mlx5e_page_cache page_cache;
|
struct hwtstamp_config *tstamp;
|
struct mlx5_clock *clock;
|
|
mlx5e_fp_handle_rx_cqe handle_rx_cqe;
|
mlx5e_fp_post_rx_wqes post_wqes;
|
mlx5e_fp_dealloc_wqe dealloc_wqe;
|
|
unsigned long state;
|
int ix;
|
unsigned int hw_mtu;
|
|
struct dim dim; /* Dynamic Interrupt Moderation */
|
|
/* XDP */
|
struct bpf_prog __rcu *xdp_prog;
|
struct mlx5e_xdpsq *xdpsq;
|
DECLARE_BITMAP(flags, 8);
|
struct page_pool *page_pool;
|
|
/* AF_XDP zero-copy */
|
struct xsk_buff_pool *xsk_pool;
|
|
struct work_struct recover_work;
|
|
/* control */
|
struct mlx5_wq_ctrl wq_ctrl;
|
__be32 mkey_be;
|
u8 wq_type;
|
u32 rqn;
|
struct mlx5_core_dev *mdev;
|
struct mlx5_core_mkey umr_mkey;
|
struct mlx5e_dma_info wqe_overflow;
|
|
/* XDP read-mostly */
|
struct xdp_rxq_info xdp_rxq;
|
} ____cacheline_aligned_in_smp;
|
|
enum mlx5e_channel_state {
|
MLX5E_CHANNEL_STATE_XSK,
|
MLX5E_CHANNEL_NUM_STATES
|
};
|
|
struct mlx5e_channel {
|
/* data path */
|
struct mlx5e_rq rq;
|
struct mlx5e_xdpsq rq_xdpsq;
|
struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
|
struct mlx5e_icosq icosq; /* internal control operations */
|
bool xdp;
|
struct napi_struct napi;
|
struct device *pdev;
|
struct net_device *netdev;
|
__be32 mkey_be;
|
u8 num_tc;
|
u8 lag_port;
|
|
/* XDP_REDIRECT */
|
struct mlx5e_xdpsq xdpsq;
|
|
/* AF_XDP zero-copy */
|
struct mlx5e_rq xskrq;
|
struct mlx5e_xdpsq xsksq;
|
|
/* Async ICOSQ */
|
struct mlx5e_icosq async_icosq;
|
/* async_icosq can be accessed from any CPU - the spinlock protects it. */
|
spinlock_t async_icosq_lock;
|
|
/* data path - accessed per napi poll */
|
struct irq_desc *irq_desc;
|
struct mlx5e_ch_stats *stats;
|
|
/* control */
|
struct mlx5e_priv *priv;
|
struct mlx5_core_dev *mdev;
|
struct hwtstamp_config *tstamp;
|
DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
|
int ix;
|
int cpu;
|
};
|
|
struct mlx5e_channels {
|
struct mlx5e_channel **c;
|
unsigned int num;
|
struct mlx5e_params params;
|
};
|
|
struct mlx5e_channel_stats {
|
struct mlx5e_ch_stats ch;
|
struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
|
struct mlx5e_rq_stats rq;
|
struct mlx5e_rq_stats xskrq;
|
struct mlx5e_xdpsq_stats rq_xdpsq;
|
struct mlx5e_xdpsq_stats xdpsq;
|
struct mlx5e_xdpsq_stats xsksq;
|
} ____cacheline_aligned_in_smp;
|
|
enum {
|
MLX5E_STATE_OPENED,
|
MLX5E_STATE_DESTROYING,
|
MLX5E_STATE_XDP_TX_ENABLED,
|
MLX5E_STATE_XDP_ACTIVE,
|
};
|
|
struct mlx5e_rqt {
|
u32 rqtn;
|
bool enabled;
|
};
|
|
struct mlx5e_tir {
|
u32 tirn;
|
struct mlx5e_rqt rqt;
|
struct list_head list;
|
};
|
|
enum {
|
MLX5E_TC_PRIO = 0,
|
MLX5E_NIC_PRIO
|
};
|
|
struct mlx5e_rss_params {
|
u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
|
u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
|
u8 toeplitz_hash_key[40];
|
u8 hfunc;
|
};
|
|
struct mlx5e_modify_sq_param {
|
int curr_state;
|
int next_state;
|
int rl_update;
|
int rl_index;
|
};
|
|
#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
|
struct mlx5e_hv_vhca_stats_agent {
|
struct mlx5_hv_vhca_agent *agent;
|
struct delayed_work work;
|
u16 delay;
|
void *buf;
|
};
|
#endif
|
|
struct mlx5e_xsk {
|
/* XSK buffer pools are stored separately from channels,
|
* because we don't want to lose them when channels are
|
* recreated. The kernel also stores buffer pool, but it doesn't
|
* distinguish between zero-copy and non-zero-copy UMEMs, so
|
* rely on our mechanism.
|
*/
|
struct xsk_buff_pool **pools;
|
u16 refcnt;
|
bool ever_used;
|
};
|
|
/* Temporary storage for variables that are allocated when struct mlx5e_priv is
|
* initialized, and used where we can't allocate them because that functions
|
* must not fail. Use with care and make sure the same variable is not used
|
* simultaneously by multiple users.
|
*/
|
struct mlx5e_scratchpad {
|
cpumask_var_t cpumask;
|
};
|
|
struct mlx5e_priv {
|
/* priv data path fields - start */
|
struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
|
int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
|
#ifdef CONFIG_MLX5_CORE_EN_DCB
|
struct mlx5e_dcbx_dp dcbx_dp;
|
#endif
|
/* priv data path fields - end */
|
|
u32 msglevel;
|
unsigned long state;
|
struct mutex state_lock; /* Protects Interface state */
|
struct mlx5e_rq drop_rq;
|
|
struct mlx5e_channels channels;
|
u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
|
struct mlx5e_rqt indir_rqt;
|
struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
|
struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
|
struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
|
struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
|
struct mlx5e_rss_params rss_params;
|
u32 tx_rates[MLX5E_MAX_NUM_SQS];
|
|
struct mlx5e_flow_steering fs;
|
|
struct workqueue_struct *wq;
|
struct work_struct update_carrier_work;
|
struct work_struct set_rx_mode_work;
|
struct work_struct tx_timeout_work;
|
struct work_struct update_stats_work;
|
struct work_struct monitor_counters_work;
|
struct mlx5_nb monitor_counters_nb;
|
|
struct mlx5_core_dev *mdev;
|
struct net_device *netdev;
|
struct mlx5e_stats stats;
|
struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
|
u16 max_nch;
|
u8 max_opened_tc;
|
struct hwtstamp_config tstamp;
|
u16 q_counter;
|
u16 drop_rq_q_counter;
|
struct notifier_block events_nb;
|
|
struct udp_tunnel_nic_info nic_info;
|
#ifdef CONFIG_MLX5_CORE_EN_DCB
|
struct mlx5e_dcbx dcbx;
|
#endif
|
|
const struct mlx5e_profile *profile;
|
void *ppriv;
|
#ifdef CONFIG_MLX5_EN_IPSEC
|
struct mlx5e_ipsec *ipsec;
|
#endif
|
#ifdef CONFIG_MLX5_EN_TLS
|
struct mlx5e_tls *tls;
|
#endif
|
struct devlink_health_reporter *tx_reporter;
|
struct devlink_health_reporter *rx_reporter;
|
struct devlink_port dl_port;
|
struct mlx5e_xsk xsk;
|
#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
|
struct mlx5e_hv_vhca_stats_agent stats_agent;
|
#endif
|
struct mlx5e_scratchpad scratchpad;
|
};
|
|
struct mlx5e_rx_handlers {
|
mlx5e_fp_handle_rx_cqe handle_rx_cqe;
|
mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
|
};
|
|
extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic;
|
|
struct mlx5e_profile {
|
int (*init)(struct mlx5_core_dev *mdev,
|
struct net_device *netdev,
|
const struct mlx5e_profile *profile, void *ppriv);
|
void (*cleanup)(struct mlx5e_priv *priv);
|
int (*init_rx)(struct mlx5e_priv *priv);
|
void (*cleanup_rx)(struct mlx5e_priv *priv);
|
int (*init_tx)(struct mlx5e_priv *priv);
|
void (*cleanup_tx)(struct mlx5e_priv *priv);
|
void (*enable)(struct mlx5e_priv *priv);
|
void (*disable)(struct mlx5e_priv *priv);
|
int (*update_rx)(struct mlx5e_priv *priv);
|
void (*update_stats)(struct mlx5e_priv *priv);
|
void (*update_carrier)(struct mlx5e_priv *priv);
|
unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);
|
mlx5e_stats_grp_t *stats_grps;
|
const struct mlx5e_rx_handlers *rx_handlers;
|
int max_tc;
|
u8 rq_groups;
|
};
|
|
void mlx5e_build_ptys2ethtool_map(void);
|
|
bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
|
bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
|
struct mlx5e_params *params);
|
|
void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
|
void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
|
|
void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
|
int mlx5e_self_test_num(struct mlx5e_priv *priv);
|
void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
|
u64 *buf);
|
void mlx5e_set_rx_mode_work(struct work_struct *work);
|
|
int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
|
int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
|
int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
|
|
int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
|
u16 vid);
|
int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
|
u16 vid);
|
void mlx5e_timestamp_init(struct mlx5e_priv *priv);
|
|
struct mlx5e_redirect_rqt_param {
|
bool is_rss;
|
union {
|
u32 rqn; /* Direct RQN (Non-RSS) */
|
struct {
|
u8 hfunc;
|
struct mlx5e_channels *channels;
|
} rss; /* RSS data */
|
};
|
};
|
|
int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
|
struct mlx5e_redirect_rqt_param rrp);
|
void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
|
const struct mlx5e_tirc_config *ttconfig,
|
void *tirc, bool inner);
|
void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in);
|
struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
|
|
struct mlx5e_xsk_param;
|
|
struct mlx5e_rq_param;
|
int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
|
struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
|
struct xsk_buff_pool *xsk_pool, struct mlx5e_rq *rq);
|
int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
|
void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
|
void mlx5e_close_rq(struct mlx5e_rq *rq);
|
|
struct mlx5e_sq_param;
|
int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
|
struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool,
|
struct mlx5e_xdpsq *sq, bool is_redirect);
|
void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
|
|
struct mlx5e_cq_param;
|
int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
|
struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
|
void mlx5e_close_cq(struct mlx5e_cq *cq);
|
|
int mlx5e_open_locked(struct net_device *netdev);
|
int mlx5e_close_locked(struct net_device *netdev);
|
|
int mlx5e_open_channels(struct mlx5e_priv *priv,
|
struct mlx5e_channels *chs);
|
void mlx5e_close_channels(struct mlx5e_channels *chs);
|
|
/* Function pointer to be used to modify HW or kernel settings while
|
* switching channels
|
*/
|
typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context);
|
#define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \
|
int fn##_ctx(struct mlx5e_priv *priv, void *context) \
|
{ \
|
return fn(priv); \
|
}
|
int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
|
int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
|
struct mlx5e_channels *new_chs,
|
mlx5e_fp_preactivate preactivate,
|
void *context);
|
int mlx5e_num_channels_changed(struct mlx5e_priv *priv);
|
int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context);
|
void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
|
void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
|
|
void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
|
int num_channels);
|
|
void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
|
void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode);
|
void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
|
void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode);
|
|
void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
|
void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
|
struct mlx5e_params *params);
|
int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
|
void mlx5e_activate_rq(struct mlx5e_rq *rq);
|
void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
|
void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
|
void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
|
|
int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
|
struct mlx5e_modify_sq_param *p);
|
void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
|
void mlx5e_tx_disable_queue(struct netdev_queue *txq);
|
|
static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
|
{
|
return MLX5_CAP_ETH(mdev, swp) &&
|
MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
|
}
|
|
extern const struct ethtool_ops mlx5e_ethtool_ops;
|
|
int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir,
|
u32 *in);
|
void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
|
struct mlx5e_tir *tir);
|
int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
|
void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
|
int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
|
bool enable_mc_lb);
|
void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc);
|
|
/* common netdev helpers */
|
void mlx5e_create_q_counters(struct mlx5e_priv *priv);
|
void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
|
int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
|
struct mlx5e_rq *drop_rq);
|
void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
|
|
int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
|
|
int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
|
void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
|
|
int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
|
void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
|
int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
|
void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
|
void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
|
|
int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
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void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
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int mlx5e_create_tises(struct mlx5e_priv *priv);
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void mlx5e_destroy_tises(struct mlx5e_priv *priv);
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int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
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void mlx5e_update_carrier(struct mlx5e_priv *priv);
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int mlx5e_close(struct net_device *netdev);
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int mlx5e_open(struct net_device *netdev);
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void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
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int mlx5e_bits_invert(unsigned long a, int size);
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int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
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int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context);
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int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
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mlx5e_fp_preactivate preactivate);
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void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv);
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/* ethtool helpers */
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void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
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struct ethtool_drvinfo *drvinfo);
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void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
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uint32_t stringset, uint8_t *data);
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int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
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void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
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struct ethtool_stats *stats, u64 *data);
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void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
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struct ethtool_ringparam *param);
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int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
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struct ethtool_ringparam *param);
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void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
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struct ethtool_channels *ch);
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int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
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struct ethtool_channels *ch);
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int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
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struct ethtool_coalesce *coal);
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int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
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struct ethtool_coalesce *coal);
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int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
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struct ethtool_link_ksettings *link_ksettings);
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int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
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const struct ethtool_link_ksettings *link_ksettings);
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int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc);
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int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
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const u8 hfunc);
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int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
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u32 *rule_locs);
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int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd);
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u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
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u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
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int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
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struct ethtool_ts_info *info);
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int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
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struct ethtool_flash *flash);
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void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
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struct ethtool_pauseparam *pauseparam);
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int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
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struct ethtool_pauseparam *pauseparam);
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/* mlx5e generic netdev management API */
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int mlx5e_netdev_init(struct net_device *netdev,
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struct mlx5e_priv *priv,
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struct mlx5_core_dev *mdev,
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const struct mlx5e_profile *profile,
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void *ppriv);
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void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
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struct net_device*
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mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
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int nch, void *ppriv);
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int mlx5e_attach_netdev(struct mlx5e_priv *priv);
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void mlx5e_detach_netdev(struct mlx5e_priv *priv);
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void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
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void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
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void mlx5e_build_nic_params(struct mlx5e_priv *priv,
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struct mlx5e_xsk *xsk,
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struct mlx5e_rss_params *rss_params,
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struct mlx5e_params *params,
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u16 mtu);
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void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
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struct mlx5e_params *params);
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void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
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u16 num_channels);
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void mlx5e_rx_dim_work(struct work_struct *work);
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void mlx5e_tx_dim_work(struct work_struct *work);
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netdev_features_t mlx5e_features_check(struct sk_buff *skb,
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struct net_device *netdev,
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netdev_features_t features);
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int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
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#ifdef CONFIG_MLX5_ESWITCH
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int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
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int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
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int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
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int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
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#endif
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#endif /* __MLX5_EN_H__ */
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