/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Cavium, Inc.
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*/
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#ifndef NIC_H
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#define NIC_H
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include "thunder_bgx.h"
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/* PCI device IDs */
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#define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
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#define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
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#define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
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#define PCI_DEVICE_ID_THUNDER_BGX 0xA026
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/* Subsystem device IDs */
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#define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
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#define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E
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#define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E
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#define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E
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#define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134
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#define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234
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#define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334
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/* PCI BAR nos */
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#define PCI_CFG_REG_BAR_NUM 0
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#define PCI_MSIX_REG_BAR_NUM 4
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/* NIC SRIOV VF count */
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#define MAX_NUM_VFS_SUPPORTED 128
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#define DEFAULT_NUM_VF_ENABLED 8
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#define NIC_TNS_BYPASS_MODE 0
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#define NIC_TNS_MODE 1
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/* NIC priv flags */
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#define NIC_SRIOV_ENABLED BIT(0)
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/* Min/Max packet size */
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#define NIC_HW_MIN_FRS 64
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#define NIC_HW_MAX_FRS 9190 /* Excluding L2 header and FCS */
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/* Max pkinds */
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#define NIC_MAX_PKIND 16
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/* Max when CPI_ALG is IP diffserv */
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#define NIC_MAX_CPI_PER_LMAC 64
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/* NIC VF Interrupts */
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#define NICVF_INTR_CQ 0
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#define NICVF_INTR_SQ 1
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#define NICVF_INTR_RBDR 2
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#define NICVF_INTR_PKT_DROP 3
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#define NICVF_INTR_TCP_TIMER 4
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#define NICVF_INTR_MBOX 5
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#define NICVF_INTR_QS_ERR 6
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#define NICVF_INTR_CQ_SHIFT 0
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#define NICVF_INTR_SQ_SHIFT 8
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#define NICVF_INTR_RBDR_SHIFT 16
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#define NICVF_INTR_PKT_DROP_SHIFT 20
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#define NICVF_INTR_TCP_TIMER_SHIFT 21
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#define NICVF_INTR_MBOX_SHIFT 22
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#define NICVF_INTR_QS_ERR_SHIFT 23
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#define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
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#define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
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#define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
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#define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
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#define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
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#define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
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#define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
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/* MSI-X interrupts */
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#define NIC_PF_MSIX_VECTORS 10
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#define NIC_VF_MSIX_VECTORS 20
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#define NIC_PF_INTR_ID_ECC0_SBE 0
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#define NIC_PF_INTR_ID_ECC0_DBE 1
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#define NIC_PF_INTR_ID_ECC1_SBE 2
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#define NIC_PF_INTR_ID_ECC1_DBE 3
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#define NIC_PF_INTR_ID_ECC2_SBE 4
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#define NIC_PF_INTR_ID_ECC2_DBE 5
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#define NIC_PF_INTR_ID_ECC3_SBE 6
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#define NIC_PF_INTR_ID_ECC3_DBE 7
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#define NIC_PF_INTR_ID_MBOX0 8
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#define NIC_PF_INTR_ID_MBOX1 9
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/* Minimum FIFO level before all packets for the CQ are dropped
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*
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* This value ensures that once a packet has been "accepted"
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* for reception it will not get dropped due to non-availability
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* of CQ descriptor. An errata in HW mandates this value to be
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* atleast 0x100.
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*/
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#define NICPF_CQM_MIN_DROP_LEVEL 0x100
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/* Global timer for CQ timer thresh interrupts
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* Calculated for SCLK of 700Mhz
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* value written should be a 1/16th of what is expected
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*
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* 1 tick per 0.025usec
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*/
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#define NICPF_CLK_PER_INT_TICK 1
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/* Time to wait before we decide that a SQ is stuck.
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*
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* Since both pkt rx and tx notifications are done with same CQ,
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* when packets are being received at very high rate (eg: L2 forwarding)
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* then freeing transmitted skbs will be delayed and watchdog
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* will kick in, resetting interface. Hence keeping this value high.
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*/
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#define NICVF_TX_TIMEOUT (50 * HZ)
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struct nicvf_cq_poll {
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struct nicvf *nicvf;
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u8 cq_idx; /* Completion queue index */
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struct napi_struct napi;
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};
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#define NIC_MAX_RSS_HASH_BITS 8
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#define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
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#define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
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struct nicvf_rss_info {
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bool enable;
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#define RSS_L2_EXTENDED_HASH_ENA BIT(0)
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#define RSS_IP_HASH_ENA BIT(1)
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#define RSS_TCP_HASH_ENA BIT(2)
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#define RSS_TCP_SYN_DIS BIT(3)
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#define RSS_UDP_HASH_ENA BIT(4)
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#define RSS_L4_EXTENDED_HASH_ENA BIT(5)
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#define RSS_ROCE_ENA BIT(6)
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#define RSS_L3_BI_DIRECTION_ENA BIT(7)
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#define RSS_L4_BI_DIRECTION_ENA BIT(8)
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u64 cfg;
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u8 hash_bits;
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u16 rss_size;
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u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
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u64 key[RSS_HASH_KEY_SIZE];
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} ____cacheline_aligned_in_smp;
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struct nicvf_pfc {
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u8 autoneg;
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u8 fc_rx;
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u8 fc_tx;
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};
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enum rx_stats_reg_offset {
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RX_OCTS = 0x0,
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RX_UCAST = 0x1,
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RX_BCAST = 0x2,
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RX_MCAST = 0x3,
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RX_RED = 0x4,
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RX_RED_OCTS = 0x5,
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RX_ORUN = 0x6,
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RX_ORUN_OCTS = 0x7,
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RX_FCS = 0x8,
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RX_L2ERR = 0x9,
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RX_DRP_BCAST = 0xa,
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RX_DRP_MCAST = 0xb,
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RX_DRP_L3BCAST = 0xc,
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RX_DRP_L3MCAST = 0xd,
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RX_STATS_ENUM_LAST,
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};
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enum tx_stats_reg_offset {
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TX_OCTS = 0x0,
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TX_UCAST = 0x1,
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TX_BCAST = 0x2,
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TX_MCAST = 0x3,
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TX_DROP = 0x4,
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TX_STATS_ENUM_LAST,
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};
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struct nicvf_hw_stats {
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u64 rx_bytes;
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u64 rx_frames;
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u64 rx_ucast_frames;
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u64 rx_bcast_frames;
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u64 rx_mcast_frames;
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u64 rx_drops;
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u64 rx_drop_red;
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u64 rx_drop_red_bytes;
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u64 rx_drop_overrun;
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u64 rx_drop_overrun_bytes;
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u64 rx_drop_bcast;
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u64 rx_drop_mcast;
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u64 rx_drop_l3_bcast;
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u64 rx_drop_l3_mcast;
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u64 rx_fcs_errors;
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u64 rx_l2_errors;
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u64 tx_bytes;
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u64 tx_frames;
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u64 tx_ucast_frames;
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u64 tx_bcast_frames;
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u64 tx_mcast_frames;
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u64 tx_drops;
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};
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struct nicvf_drv_stats {
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/* CQE Rx errs */
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u64 rx_bgx_truncated_pkts;
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u64 rx_jabber_errs;
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u64 rx_fcs_errs;
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u64 rx_bgx_errs;
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u64 rx_prel2_errs;
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u64 rx_l2_hdr_malformed;
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u64 rx_oversize;
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u64 rx_undersize;
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u64 rx_l2_len_mismatch;
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u64 rx_l2_pclp;
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u64 rx_ip_ver_errs;
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u64 rx_ip_csum_errs;
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u64 rx_ip_hdr_malformed;
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u64 rx_ip_payload_malformed;
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u64 rx_ip_ttl_errs;
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u64 rx_l3_pclp;
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u64 rx_l4_malformed;
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u64 rx_l4_csum_errs;
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u64 rx_udp_len_errs;
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u64 rx_l4_port_errs;
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u64 rx_tcp_flag_errs;
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u64 rx_tcp_offset_errs;
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u64 rx_l4_pclp;
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u64 rx_truncated_pkts;
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/* CQE Tx errs */
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u64 tx_desc_fault;
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u64 tx_hdr_cons_err;
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u64 tx_subdesc_err;
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u64 tx_max_size_exceeded;
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u64 tx_imm_size_oflow;
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u64 tx_data_seq_err;
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u64 tx_mem_seq_err;
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u64 tx_lock_viol;
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u64 tx_data_fault;
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u64 tx_tstmp_conflict;
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u64 tx_tstmp_timeout;
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u64 tx_mem_fault;
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u64 tx_csum_overlap;
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u64 tx_csum_overflow;
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/* driver debug stats */
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u64 tx_tso;
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u64 tx_timeout;
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u64 txq_stop;
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u64 txq_wake;
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u64 rcv_buffer_alloc_failures;
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u64 page_alloc;
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struct u64_stats_sync syncp;
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};
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struct cavium_ptp;
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struct xcast_addr_list {
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int count;
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u64 mc[];
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};
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struct nicvf_work {
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struct work_struct work;
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u8 mode;
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struct xcast_addr_list *mc;
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};
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struct nicvf {
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struct nicvf *pnicvf;
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struct net_device *netdev;
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struct pci_dev *pdev;
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void __iomem *reg_base;
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struct bpf_prog *xdp_prog;
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#define MAX_QUEUES_PER_QSET 8
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struct queue_set *qs;
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void *iommu_domain;
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u8 vf_id;
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u8 sqs_id;
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bool sqs_mode;
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bool hw_tso;
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bool t88;
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/* Receive buffer alloc */
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u32 rb_page_offset;
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u16 rb_pageref;
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bool rb_alloc_fail;
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bool rb_work_scheduled;
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struct page *rb_page;
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struct delayed_work rbdr_work;
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struct tasklet_struct rbdr_task;
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/* Secondary Qset */
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u8 sqs_count;
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#define MAX_SQS_PER_VF_SINGLE_NODE 5
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#define MAX_SQS_PER_VF 11
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struct nicvf *snicvf[MAX_SQS_PER_VF];
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/* Queue count */
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u8 rx_queues;
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u8 tx_queues;
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u8 xdp_tx_queues;
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u8 max_queues;
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u8 node;
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u8 cpi_alg;
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bool link_up;
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u8 mac_type;
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u8 duplex;
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u32 speed;
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bool tns_mode;
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bool loopback_supported;
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struct nicvf_rss_info rss_info;
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struct nicvf_pfc pfc;
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struct tasklet_struct qs_err_task;
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struct work_struct reset_task;
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struct nicvf_work rx_mode_work;
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/* spinlock to protect workqueue arguments from concurrent access */
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spinlock_t rx_mode_wq_lock;
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/* workqueue for handling kernel ndo_set_rx_mode() calls */
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struct workqueue_struct *nicvf_rx_mode_wq;
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/* mutex to protect VF's mailbox contents from concurrent access */
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struct mutex rx_mode_mtx;
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struct delayed_work link_change_work;
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/* PTP timestamp */
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struct cavium_ptp *ptp_clock;
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/* Inbound timestamping is on */
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bool hw_rx_tstamp;
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/* When the packet that requires timestamping is sent, hardware inserts
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* two entries to the completion queue. First is the regular
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* CQE_TYPE_SEND entry that signals that the packet was sent.
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* The second is CQE_TYPE_SEND_PTP that contains the actual timestamp
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* for that packet.
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* `ptp_skb` is initialized in the handler for the CQE_TYPE_SEND
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* entry and is used and zeroed in the handler for the CQE_TYPE_SEND_PTP
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* entry.
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* So `ptp_skb` is used to hold the pointer to the packet between
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* the calls to CQE_TYPE_SEND and CQE_TYPE_SEND_PTP handlers.
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*/
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struct sk_buff *ptp_skb;
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/* `tx_ptp_skbs` is set when the hardware is sending a packet that
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* requires timestamping. Cavium hardware can not process more than one
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* such packet at once so this is set each time the driver submits
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* a packet that requires timestamping to the send queue and clears
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* each time it receives the entry on the completion queue saying
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* that such packet was sent.
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* So `tx_ptp_skbs` prevents driver from submitting more than one
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* packet that requires timestamping to the hardware for transmitting.
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*/
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atomic_t tx_ptp_skbs;
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/* Interrupt coalescing settings */
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u32 cq_coalesce_usecs;
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u32 msg_enable;
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/* Stats */
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struct nicvf_hw_stats hw_stats;
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struct nicvf_drv_stats __percpu *drv_stats;
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struct bgx_stats bgx_stats;
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/* Napi */
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struct nicvf_cq_poll *napi[8];
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/* MSI-X */
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u8 num_vec;
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char irq_name[NIC_VF_MSIX_VECTORS][IFNAMSIZ + 15];
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bool irq_allocated[NIC_VF_MSIX_VECTORS];
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cpumask_var_t affinity_mask[NIC_VF_MSIX_VECTORS];
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/* VF <-> PF mailbox communication */
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bool pf_acked;
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bool pf_nacked;
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bool set_mac_pending;
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} ____cacheline_aligned_in_smp;
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/* PF <--> VF Mailbox communication
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* Eight 64bit registers are shared between PF and VF.
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* Separate set for each VF.
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* Writing '1' into last register mbx7 means end of message.
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*/
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/* PF <--> VF mailbox communication */
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#define NIC_PF_VF_MAILBOX_SIZE 2
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#define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */
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/* Mailbox message types */
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#define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
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#define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
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#define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
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#define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
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#define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
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#define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
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#define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
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#define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
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#define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
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#define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
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#define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
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#define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
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#define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
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#define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
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#define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
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#define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
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#define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
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#define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
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#define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
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#define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
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#define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
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#define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
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#define NIC_MBOX_MSG_RESET_STAT_COUNTER 0x17 /* Reset statistics counters */
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#define NIC_MBOX_MSG_PFC 0x18 /* Pause frame control */
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#define NIC_MBOX_MSG_PTP_CFG 0x19 /* HW packet timestamp */
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#define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
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#define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
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#define NIC_MBOX_MSG_RESET_XCAST 0xF2 /* Reset DCAM filtering mode */
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#define NIC_MBOX_MSG_ADD_MCAST 0xF3 /* Add MAC to DCAM filters */
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#define NIC_MBOX_MSG_SET_XCAST 0xF4 /* Set MCAST/BCAST RX mode */
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struct nic_cfg_msg {
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u8 msg;
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u8 vf_id;
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u8 node_id;
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u8 tns_mode:1;
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u8 sqs_mode:1;
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u8 loopback_supported:1;
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u8 mac_addr[ETH_ALEN];
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};
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/* Qset configuration */
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struct qs_cfg_msg {
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u8 msg;
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u8 num;
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u8 sqs_count;
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u64 cfg;
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};
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/* Receive queue configuration */
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struct rq_cfg_msg {
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u8 msg;
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u8 qs_num;
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u8 rq_num;
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u64 cfg;
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};
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/* Send queue configuration */
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struct sq_cfg_msg {
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u8 msg;
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u8 qs_num;
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u8 sq_num;
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bool sqs_mode;
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u64 cfg;
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};
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/* Set VF's MAC address */
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struct set_mac_msg {
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u8 msg;
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u8 vf_id;
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u8 mac_addr[ETH_ALEN];
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};
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/* Set Maximum frame size */
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struct set_frs_msg {
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u8 msg;
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u8 vf_id;
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u16 max_frs;
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};
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/* Set CPI algorithm type */
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struct cpi_cfg_msg {
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u8 msg;
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u8 vf_id;
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u8 rq_cnt;
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u8 cpi_alg;
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};
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/* Get RSS table size */
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struct rss_sz_msg {
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u8 msg;
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u8 vf_id;
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u16 ind_tbl_size;
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};
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/* Set RSS configuration */
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struct rss_cfg_msg {
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u8 msg;
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u8 vf_id;
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u8 hash_bits;
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u8 tbl_len;
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u8 tbl_offset;
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#define RSS_IND_TBL_LEN_PER_MBX_MSG 8
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u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
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};
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struct bgx_stats_msg {
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u8 msg;
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u8 vf_id;
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u8 rx;
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u8 idx;
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u64 stats;
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};
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/* Physical interface link status */
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struct bgx_link_status {
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u8 msg;
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u8 mac_type;
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u8 link_up;
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u8 duplex;
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u32 speed;
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};
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/* Get Extra Qset IDs */
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struct sqs_alloc {
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u8 msg;
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u8 vf_id;
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u8 qs_count;
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};
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struct nicvf_ptr {
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u8 msg;
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u8 vf_id;
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bool sqs_mode;
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u8 sqs_id;
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u64 nicvf;
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};
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/* Set interface in loopback mode */
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struct set_loopback {
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u8 msg;
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u8 vf_id;
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bool enable;
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};
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/* Reset statistics counters */
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struct reset_stat_cfg {
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u8 msg;
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/* Bitmap to select NIC_PF_VNIC(vf_id)_RX_STAT(0..13) */
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u16 rx_stat_mask;
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/* Bitmap to select NIC_PF_VNIC(vf_id)_TX_STAT(0..4) */
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u8 tx_stat_mask;
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/* Bitmap to select NIC_PF_QS(0..127)_RQ(0..7)_STAT(0..1)
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* bit14, bit15 NIC_PF_QS(vf_id)_RQ7_STAT(0..1)
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* bit12, bit13 NIC_PF_QS(vf_id)_RQ6_STAT(0..1)
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* ..
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* bit2, bit3 NIC_PF_QS(vf_id)_RQ1_STAT(0..1)
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* bit0, bit1 NIC_PF_QS(vf_id)_RQ0_STAT(0..1)
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*/
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u16 rq_stat_mask;
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/* Bitmap to select NIC_PF_QS(0..127)_SQ(0..7)_STAT(0..1)
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* bit14, bit15 NIC_PF_QS(vf_id)_SQ7_STAT(0..1)
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* bit12, bit13 NIC_PF_QS(vf_id)_SQ6_STAT(0..1)
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* ..
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* bit2, bit3 NIC_PF_QS(vf_id)_SQ1_STAT(0..1)
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* bit0, bit1 NIC_PF_QS(vf_id)_SQ0_STAT(0..1)
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*/
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u16 sq_stat_mask;
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};
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struct pfc {
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u8 msg;
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u8 get; /* Get or set PFC settings */
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u8 autoneg;
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u8 fc_rx;
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u8 fc_tx;
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};
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struct set_ptp {
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u8 msg;
|
bool enable;
|
};
|
|
struct xcast {
|
u8 msg;
|
u8 mode;
|
u64 mac:48;
|
};
|
|
/* 128 bit shared memory between PF and each VF */
|
union nic_mbx {
|
struct { u8 msg; } msg;
|
struct nic_cfg_msg nic_cfg;
|
struct qs_cfg_msg qs;
|
struct rq_cfg_msg rq;
|
struct sq_cfg_msg sq;
|
struct set_mac_msg mac;
|
struct set_frs_msg frs;
|
struct cpi_cfg_msg cpi_cfg;
|
struct rss_sz_msg rss_size;
|
struct rss_cfg_msg rss_cfg;
|
struct bgx_stats_msg bgx_stats;
|
struct bgx_link_status link_status;
|
struct sqs_alloc sqs_alloc;
|
struct nicvf_ptr nicvf;
|
struct set_loopback lbk;
|
struct reset_stat_cfg reset_stat;
|
struct pfc pfc;
|
struct set_ptp ptp;
|
struct xcast xcast;
|
};
|
|
#define NIC_NODE_ID_MASK 0x03
|
#define NIC_NODE_ID_SHIFT 44
|
|
static inline int nic_get_node_id(struct pci_dev *pdev)
|
{
|
u64 addr = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM);
|
return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK);
|
}
|
|
static inline bool pass1_silicon(struct pci_dev *pdev)
|
{
|
return (pdev->revision < 8) &&
|
(pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
|
}
|
|
static inline bool pass2_silicon(struct pci_dev *pdev)
|
{
|
return (pdev->revision >= 8) &&
|
(pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF);
|
}
|
|
int nicvf_set_real_num_queues(struct net_device *netdev,
|
int tx_queues, int rx_queues);
|
int nicvf_open(struct net_device *netdev);
|
int nicvf_stop(struct net_device *netdev);
|
int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
|
void nicvf_config_rss(struct nicvf *nic);
|
void nicvf_set_rss_key(struct nicvf *nic);
|
void nicvf_set_ethtool_ops(struct net_device *netdev);
|
void nicvf_update_stats(struct nicvf *nic);
|
void nicvf_update_lmac_stats(struct nicvf *nic);
|
|
#endif /* NIC_H */
|
