/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2020 Rockchip Electronics Co., Ltd. */
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#ifndef _RKISPP_HW_H
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#define _RKISPP_HW_H
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#include "common.h"
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#include "fec.h"
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#include "../isp/isp_ispp.h"
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#define ISPP_MAX_BUS_CLK 4
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struct ispp_clk_info {
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u32 clk_rate;
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u32 refer_data;
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};
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struct ispp_match_data {
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int clks_num;
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const char * const *clks;
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int clk_rate_tbl_num;
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const struct ispp_clk_info *clk_rate_tbl;
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enum rkispp_ver ispp_ver;
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struct irqs_data *irqs;
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int num_irqs;
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};
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struct rkispp_hw_dev {
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struct device *dev;
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void __iomem *base_addr;
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const struct ispp_match_data *match_data;
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const struct ispp_clk_info *clk_rate_tbl;
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struct reset_control *reset;
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struct clk *clks[ISPP_MAX_BUS_CLK];
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struct rkispp_device *ispp[DEV_MAX];
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struct rkispp_isp_buf_pool pool[RKISPP_BUF_POOL_MAX];
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struct rkispp_dummy_buffer dummy_buf;
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struct rkispp_fec_dev fec_dev;
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struct max_input max_in;
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struct list_head list;
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int clk_rate_tbl_num;
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int clks_num;
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int dev_num;
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int cur_dev_id;
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unsigned long core_clk_min;
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unsigned long core_clk_max;
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enum rkispp_ver ispp_ver;
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/* lock for irq */
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spinlock_t irq_lock;
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/* lock for multi dev */
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struct mutex dev_lock;
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spinlock_t buf_lock;
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atomic_t refcnt;
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const struct vb2_mem_ops *mem_ops;
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struct rkisp_ispp_reg *reg_buf;
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bool is_mmu;
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bool is_idle;
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bool is_single;
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bool is_fec_ext;
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bool is_dma_contig;
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bool is_dma_sg_ops;
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bool is_shutdown;
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bool is_first;
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};
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void rkispp_soft_reset(struct rkispp_hw_dev *hw_dev);
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#endif
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