// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2020 Rockchip Electronics Co., Ltd */
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iommu.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/of_platform.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include <media/videobuf2-cma-sg.h>
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#include <media/videobuf2-dma-sg.h>
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#include <soc/rockchip/rockchip_iommu.h>
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#include "common.h"
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#include "dev.h"
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#include "fec.h"
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#include "hw.h"
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#include "regs.h"
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/*
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* rkispp_hw share hardware resource with rkispp virtual device
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* rkispp_device rkispp_device rkispp_device rkispp_device
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* | | | |
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* \ | | /
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* -----------------------------------------
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* |
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* rkispp_hw
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*/
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struct irqs_data {
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const char *name;
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irqreturn_t (*irq_hdl)(int irq, void *ctx);
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};
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void rkispp_soft_reset(struct rkispp_hw_dev *hw)
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{
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writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
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udelay(10);
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writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
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if (hw->reset) {
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reset_control_assert(hw->reset);
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udelay(20);
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reset_control_deassert(hw->reset);
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udelay(20);
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}
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/* refresh iommu after reset */
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if (hw->is_mmu) {
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rockchip_iommu_disable(hw->dev);
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rockchip_iommu_enable(hw->dev);
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}
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if (hw->ispp_ver == ISPP_V10) {
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writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
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writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
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writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
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writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
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writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
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FBCH_EMPTY_TNR | FBCD_DEC_ERR_NR | FBCD_DEC_ERR_TNR |
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BUS_ERR_NR | BUS_ERR_TNR | SCL2_INT | SCL1_INT |
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SCL0_INT | FEC_INT | ORB_INT | SHP_INT | NR_INT | TNR_INT,
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hw->base_addr + RKISPP_CTRL_INT_MSK);
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writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
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} else if (hw->ispp_ver == ISPP_V20) {
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writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
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writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
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writel(FEC_INT, hw->base_addr + RKISPP_CTRL_INT_MSK);
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writel(GATE_DIS_FEC, hw->base_addr + RKISPP_CTRL_CLKGATE);
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}
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}
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/* using default value if reg no write for multi device */
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static void default_sw_reg_flag(struct rkispp_device *dev)
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{
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if (dev->hw_dev->ispp_ver == ISPP_V10) {
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u32 reg[] = {
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RKISPP_TNR_CTRL,
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RKISPP_TNR_CORE_CTRL,
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RKISPP_NR_CTRL,
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RKISPP_NR_UVNR_CTRL_PARA,
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RKISPP_SHARP_CTRL,
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RKISPP_SHARP_CORE_CTRL,
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RKISPP_SCL0_CTRL,
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RKISPP_SCL1_CTRL,
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RKISPP_SCL2_CTRL,
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RKISPP_ORB_CORE_CTRL,
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RKISPP_FEC_CTRL,
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RKISPP_FEC_CORE_CTRL
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};
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u32 i, *flag;
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for (i = 0; i < ARRAY_SIZE(reg); i++) {
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flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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*flag = 0xffffffff;
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}
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} else if (dev->hw_dev->ispp_ver == ISPP_V20) {
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u32 reg[] = {
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RKISPP_FEC_CTRL,
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RKISPP_FEC_CORE_CTRL
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};
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u32 i, *flag;
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for (i = 0; i < ARRAY_SIZE(reg); i++) {
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flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
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*flag = 0xffffffff;
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}
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}
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}
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static inline bool is_iommu_enable(struct device *dev)
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{
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struct device_node *iommu;
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iommu = of_parse_phandle(dev->of_node, "iommus", 0);
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if (!iommu) {
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dev_info(dev, "no iommu attached, using non-iommu buffers\n");
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return false;
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} else if (!of_device_is_available(iommu)) {
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dev_info(dev, "iommu is disabled, using non-iommu buffers\n");
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of_node_put(iommu);
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return false;
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}
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of_node_put(iommu);
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return true;
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}
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static void disable_sys_clk(struct rkispp_hw_dev *dev)
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{
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int i;
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for (i = 0; i < dev->clks_num; i++)
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clk_disable_unprepare(dev->clks[i]);
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}
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static int enable_sys_clk(struct rkispp_hw_dev *dev)
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{
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struct rkispp_device *ispp = dev->ispp[dev->cur_dev_id];
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int w, i, ret = -EINVAL;
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for (i = 0; i < dev->clks_num; i++) {
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ret = clk_prepare_enable(dev->clks[i]);
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if (ret < 0)
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goto err;
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}
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if (!ispp)
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return ret;
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w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
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for (i = 0; i < dev->clk_rate_tbl_num; i++)
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if (w <= dev->clk_rate_tbl[i].refer_data)
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break;
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if (!dev->is_single)
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i++;
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if (i > dev->clk_rate_tbl_num - 1)
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i = dev->clk_rate_tbl_num - 1;
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dev->core_clk_max = dev->clk_rate_tbl[i].clk_rate * 1000000;
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dev->core_clk_min = dev->clk_rate_tbl[0].clk_rate * 1000000;
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rkispp_set_clk_rate(dev->clks[0], dev->core_clk_min);
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dev_dbg(dev->dev, "set ispp clk:%luHz\n", clk_get_rate(dev->clks[0]));
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return 0;
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err:
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for (--i; i >= 0; --i)
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clk_disable_unprepare(dev->clks[i]);
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return ret;
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}
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static irqreturn_t irq_hdl(int irq, void *ctx)
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{
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struct device *dev = ctx;
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struct rkispp_hw_dev *hw_dev = dev_get_drvdata(dev);
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struct rkispp_device *ispp = hw_dev->ispp[hw_dev->cur_dev_id];
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void __iomem *base = hw_dev->base_addr;
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unsigned int mis_val;
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spin_lock(&hw_dev->irq_lock);
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mis_val = readl(base + RKISPP_CTRL_INT_STA);
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writel(mis_val, base + RKISPP_CTRL_INT_CLR);
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spin_unlock(&hw_dev->irq_lock);
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if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISPP_FEC) && mis_val & FEC_INT) {
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mis_val &= ~FEC_INT;
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rkispp_fec_irq(hw_dev);
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}
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if (mis_val)
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ispp->irq_hdl(mis_val, ispp);
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return IRQ_HANDLED;
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}
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static const char * const rv1126_ispp_clks[] = {
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"clk_ispp",
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"aclk_ispp",
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"hclk_ispp",
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};
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static const char * const rk3588_ispp_clks[] = {
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"clk_ispp",
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"aclk_ispp",
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"hclk_ispp",
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};
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static const struct ispp_clk_info rv1126_ispp_clk_rate[] = {
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{
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.clk_rate = 150,
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.refer_data = 0,
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}, {
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.clk_rate = 250,
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.refer_data = 1920 //width
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}, {
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.clk_rate = 350,
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.refer_data = 2688,
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}, {
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.clk_rate = 400,
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.refer_data = 3072,
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}, {
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.clk_rate = 500,
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.refer_data = 3840,
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}
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};
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static const struct ispp_clk_info rk3588_ispp_clk_rate[] = {
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{
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.clk_rate = 300,
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.refer_data = 1920, //width
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}, {
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.clk_rate = 400,
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.refer_data = 2688,
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}, {
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.clk_rate = 500,
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.refer_data = 3072,
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}, {
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.clk_rate = 600,
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.refer_data = 3840,
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}, {
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.clk_rate = 702,
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.refer_data = 4672,
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}
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};
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static struct irqs_data rv1126_ispp_irqs[] = {
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{"ispp_irq", irq_hdl},
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{"fec_irq", irq_hdl},
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};
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static struct irqs_data rk3588_ispp_irqs[] = {
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{"fec_irq", irq_hdl},
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};
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static const struct ispp_match_data rv1126_ispp_match_data = {
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.clks = rv1126_ispp_clks,
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.clks_num = ARRAY_SIZE(rv1126_ispp_clks),
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.clk_rate_tbl = rv1126_ispp_clk_rate,
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.clk_rate_tbl_num = ARRAY_SIZE(rv1126_ispp_clk_rate),
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.irqs = rv1126_ispp_irqs,
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.num_irqs = ARRAY_SIZE(rv1126_ispp_irqs),
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.ispp_ver = ISPP_V10,
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};
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static const struct ispp_match_data rk3588_ispp_match_data = {
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.clks = rk3588_ispp_clks,
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.clks_num = ARRAY_SIZE(rk3588_ispp_clks),
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.clk_rate_tbl = rk3588_ispp_clk_rate,
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.clk_rate_tbl_num = ARRAY_SIZE(rk3588_ispp_clk_rate),
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.irqs = rk3588_ispp_irqs,
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.num_irqs = ARRAY_SIZE(rk3588_ispp_irqs),
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.ispp_ver = ISPP_V20,
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};
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static const struct of_device_id rkispp_hw_of_match[] = {
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{
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.compatible = "rockchip,rv1126-rkispp",
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.data = &rv1126_ispp_match_data,
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}, {
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.compatible = "rockchip,rk3588-rkispp",
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.data = &rk3588_ispp_match_data,
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},
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{},
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};
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static int rkispp_hw_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct ispp_match_data *match_data;
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struct device_node *node = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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struct rkispp_hw_dev *hw_dev;
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struct resource *res;
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int i, ret, irq;
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bool is_mem_reserved = true;
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match = of_match_node(rkispp_hw_of_match, node);
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if (IS_ERR(match))
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return PTR_ERR(match);
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hw_dev = devm_kzalloc(dev, sizeof(*hw_dev), GFP_KERNEL);
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if (!hw_dev)
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return -ENOMEM;
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dev_set_drvdata(dev, hw_dev);
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hw_dev->dev = dev;
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match_data = match->data;
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hw_dev->match_data = match->data;
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hw_dev->max_in.w = 0;
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hw_dev->max_in.h = 0;
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hw_dev->max_in.fps = 0;
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of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3);
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dev_info(dev, "max input:%dx%d@%dfps\n",
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hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "get resource failed\n");
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ret = -EINVAL;
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goto err;
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}
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hw_dev->base_addr = devm_ioremap_resource(dev, res);
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if (PTR_ERR(hw_dev->base_addr) == -EBUSY) {
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resource_size_t offset = res->start;
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resource_size_t size = resource_size(res);
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hw_dev->base_addr = devm_ioremap(dev, offset, size);
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}
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if (IS_ERR(hw_dev->base_addr)) {
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dev_err(dev, "ioremap failed\n");
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ret = PTR_ERR(hw_dev->base_addr);
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goto err;
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}
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rkispp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
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res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
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match_data->irqs[0].name);
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if (res) {
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/* there are irq names in dts */
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for (i = 0; i < match_data->num_irqs; i++) {
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irq = platform_get_irq_byname(pdev,
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match_data->irqs[i].name);
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if (irq < 0) {
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dev_err(dev, "no irq %s in dts\n",
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match_data->irqs[i].name);
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ret = irq;
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goto err;
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}
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ret = devm_request_irq(dev, irq,
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match_data->irqs[i].irq_hdl,
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IRQF_SHARED,
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dev_driver_string(dev),
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dev);
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if (ret < 0) {
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dev_err(dev, "request %s failed: %d\n",
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match_data->irqs[i].name, ret);
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goto err;
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}
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}
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}
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for (i = 0; i < match_data->clks_num; i++) {
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struct clk *clk = devm_clk_get(dev, match_data->clks[i]);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get %s\n",
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match_data->clks[i]);
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ret = PTR_ERR(clk);
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goto err;
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}
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hw_dev->clks[i] = clk;
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}
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hw_dev->clks_num = match_data->clks_num;
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hw_dev->clk_rate_tbl = match_data->clk_rate_tbl;
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hw_dev->clk_rate_tbl_num = match_data->clk_rate_tbl_num;
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hw_dev->reset = devm_reset_control_array_get(dev, false, false);
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if (IS_ERR(hw_dev->reset)) {
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dev_info(dev, "failed to get cru reset\n");
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hw_dev->reset = NULL;
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}
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hw_dev->dev_num = 0;
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hw_dev->cur_dev_id = 0;
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hw_dev->ispp_ver = match_data->ispp_ver;
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mutex_init(&hw_dev->dev_lock);
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spin_lock_init(&hw_dev->irq_lock);
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spin_lock_init(&hw_dev->buf_lock);
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atomic_set(&hw_dev->refcnt, 0);
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INIT_LIST_HEAD(&hw_dev->list);
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hw_dev->is_idle = true;
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hw_dev->is_single = true;
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/* for frame end reset and config reg */
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if (hw_dev->ispp_ver == ISPP_V10)
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hw_dev->is_single = false;
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hw_dev->is_fec_ext = false;
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hw_dev->is_dma_contig = true;
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hw_dev->is_dma_sg_ops = true;
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hw_dev->is_shutdown = false;
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hw_dev->is_first = true;
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hw_dev->is_mmu = is_iommu_enable(dev);
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ret = of_reserved_mem_device_init(dev);
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if (ret) {
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is_mem_reserved = false;
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if (!hw_dev->is_mmu)
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dev_info(dev, "No reserved memory region. default cma area!\n");
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}
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if (hw_dev->is_mmu && !is_mem_reserved)
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hw_dev->is_dma_contig = false;
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hw_dev->mem_ops = &vb2_cma_sg_memops;
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rkispp_register_fec(hw_dev);
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pm_runtime_enable(&pdev->dev);
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return 0;
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err:
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return ret;
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}
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static int rkispp_hw_remove(struct platform_device *pdev)
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{
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struct rkispp_hw_dev *hw_dev = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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mutex_destroy(&hw_dev->dev_lock);
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rkispp_unregister_fec(hw_dev);
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return 0;
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}
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static void rkispp_hw_shutdown(struct platform_device *pdev)
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{
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struct rkispp_hw_dev *hw_dev = platform_get_drvdata(pdev);
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hw_dev->is_shutdown = true;
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if (pm_runtime_active(&pdev->dev)) {
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writel(0, hw_dev->base_addr + RKISPP_CTRL_INT_MSK);
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writel(GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
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writel(~GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
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}
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dev_info(&pdev->dev, "%s\n", __func__);
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}
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static int __maybe_unused rkispp_runtime_suspend(struct device *dev)
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{
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struct rkispp_hw_dev *hw_dev = dev_get_drvdata(dev);
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writel(0, hw_dev->base_addr + RKISPP_CTRL_INT_MSK);
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disable_sys_clk(hw_dev);
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return 0;
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}
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static int __maybe_unused rkispp_runtime_resume(struct device *dev)
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{
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struct rkispp_hw_dev *hw_dev = dev_get_drvdata(dev);
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void __iomem *base = hw_dev->base_addr;
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int i;
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enable_sys_clk(hw_dev);
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rkispp_soft_reset(hw_dev);
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for (i = 0; i < hw_dev->dev_num; i++) {
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void *buf = hw_dev->ispp[i]->sw_base_addr;
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memset(buf, 0, RKISP_ISPP_SW_MAX_SIZE);
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memcpy_fromio(buf, base, RKISP_ISPP_SW_REG_SIZE);
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default_sw_reg_flag(hw_dev->ispp[i]);
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}
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hw_dev->is_idle = true;
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return 0;
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}
|
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static const struct dev_pm_ops rkispp_hw_pm_ops = {
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SET_RUNTIME_PM_OPS(rkispp_runtime_suspend,
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rkispp_runtime_resume, NULL)
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};
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static struct platform_driver rkispp_hw_drv = {
|
.driver = {
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.name = "rkispp_hw",
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.of_match_table = of_match_ptr(rkispp_hw_of_match),
|
.pm = &rkispp_hw_pm_ops,
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},
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.probe = rkispp_hw_probe,
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.remove = rkispp_hw_remove,
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.shutdown = rkispp_hw_shutdown,
|
};
|
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int __init rkispp_hw_drv_init(void)
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{
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int ret;
|
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ret = platform_driver_register(&rkispp_hw_drv);
|
if (!ret)
|
ret = platform_driver_register(&rkispp_plat_drv);
|
return ret;
|
}
|
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#if !(IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISP) && IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISPP))
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module_init(rkispp_hw_drv_init);
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#endif
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