/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#ifndef RK628_CRU_H
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#define RK628_CRU_H
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#include "rk628.h"
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#define CRU_REG(x) ((x) + 0xc0000)
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#define CRU_CPLL_CON0 CRU_REG(0x0000)
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#define PLL_BYPASS_MASK BIT(15)
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#define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15)
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#define PLL_BYPASS_SHIFT 15
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#define PLL_POSTDIV1_MASK GENMASK(14, 12)
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#define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12)
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#define PLL_POSTDIV1_SHIFT 12
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#define PLL_FBDIV_MASK GENMASK(11, 0)
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#define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0)
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#define PLL_FBDIV_SHIFT 0
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#define CRU_CPLL_CON1 CRU_REG(0x0004)
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#define PLL_PD_MASK BIT(13)
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#define PLL_PD(x) HIWORD_UPDATE(x, 13, 13)
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#define PLL_DSMPD_MASK BIT(12)
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#define PLL_DSMPD(x) HIWORD_UPDATE(x, 12, 12)
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#define PLL_DSMPD_SHIFT 12
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#define PLL_LOCK BIT(10)
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#define PLL_POSTDIV2_MASK GENMASK(8, 6)
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#define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6)
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#define PLL_POSTDIV2_SHIFT 6
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#define PLL_REFDIV_MASK GENMASK(5, 0)
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#define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0)
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#define PLL_REFDIV_SHIFT 0
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#define CRU_CPLL_CON2 CRU_REG(0x0008)
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#define PLL_FRAC_MASK GENMASK(23, 0)
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#define PLL_FRAC(x) ((x) << 0)
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#define PLL_FRAC_SHIFT 0
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#define CRU_CPLL_CON3 CRU_REG(0x000c)
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#define CRU_CPLL_CON4 CRU_REG(0x0010)
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#define CRU_GPLL_CON0 CRU_REG(0x0020)
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#define CRU_GPLL_CON1 CRU_REG(0x0024)
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#define CRU_GPLL_CON2 CRU_REG(0x0028)
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#define CRU_GPLL_CON3 CRU_REG(0x002c)
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#define CRU_GPLL_CON4 CRU_REG(0x0030)
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#define CRU_MODE_CON00 CRU_REG(0x0060)
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#define CLK_GPLL_MODE_MASK BIT(2)
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#define CLK_GPLL_MODE_SHIFT 2
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#define CLK_GPLL_MODE_GPLL 1
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#define CLK_GPLL_MODE_OSC 0
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#define CLK_CPLL_MODE_MASK BIT(0)
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#define CLK_CPLL_MODE_SHIFT 0
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#define CLK_CPLL_MODE_CPLL 1
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#define CLK_CPLL_MODE_OSC 0
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#define CRU_CLKSEL_CON00 CRU_REG(0x0080)
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#define CRU_CLKSEL_CON01 CRU_REG(0x0084)
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#define CRU_CLKSEL_CON02 CRU_REG(0x0088)
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#define SCLK_VOP_SEL_MASK BIT(9)
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#define SCLK_VOP_SEL_SHIFT 9
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#define SCLK_VOP_SEL_GPLL 1
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#define SCLK_VOP_SEL_CPLL 0
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#define CLK_RX_READ_SEL_MASK BIT(8)
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#define CLK_RX_READ_SEL_SHIFT 8
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#define CLK_RX_READ_SEL_GPLL 1
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#define CLK_RX_READ_SEL_CPLL 0
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#define CRU_CLKSEL_CON03 CRU_REG(0x008c)
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#define CRU_CLKSEL_CON04 CRU_REG(0x0090)
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#define CRU_CLKSEL_CON05 CRU_REG(0x0094)
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#define CLK_HDMIRX_AUD_SEL BIT(15)
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#define CRU_CLKSEL_CON06 CRU_REG(0x0098)
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#define SCLK_UART_SEL(x) HIWORD_UPDATE(x, 15, 14)
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#define SCLK_UART_SEL_MASK GENMASK(15, 14)
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#define SCLK_UART_SEL_SHIFT 14
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#define SCLK_UART_SEL_OSC 2
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#define SCLK_UART_SEL_UART_FRAC 1
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#define SCLK_UART_SEL_UART_SRC 0
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#define CRU_CLKSEL_CON07 CRU_REG(0x009c)
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#define CRU_CLKSEL_CON08 CRU_REG(0x00a0)
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#define CRU_CLKSEL_CON09 CRU_REG(0x00a4)
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#define CRU_CLKSEL_CON10 CRU_REG(0x00a8)
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#define CRU_CLKSEL_CON11 CRU_REG(0x00ac)
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#define CRU_CLKSEL_CON12 CRU_REG(0x00b0)
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#define CRU_CLKSEL_CON13 CRU_REG(0x00b4)
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#define CRU_CLKSEL_CON14 CRU_REG(0x00b8)
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#define CRU_CLKSEL_CON15 CRU_REG(0x00bc)
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#define CRU_CLKSEL_CON16 CRU_REG(0x00c0)
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#define CRU_CLKSEL_CON17 CRU_REG(0x00c4)
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#define CRU_CLKSEL_CON18 CRU_REG(0x00c8)
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#define CRU_CLKSEL_CON20 CRU_REG(0x00d0)
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#define CRU_CLKSEL_CON21 CRU_REG(0x00d4)
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#define CLK_UART_SRC_SEL_MASK BIT(15)
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#define CLK_UART_SRC_SEL_GPLL (1 << 15)
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#define CLK_UART_SRC_SEL_CPLL (0 << 15)
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#define CLK_UART_SRC_DIV_MASK GENMASK(12, 8)
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#define CLK_UART_SRC_DIV_SHIFT 8
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#define CRU_GATE_CON00 CRU_REG(0x0180)
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#define CRU_GATE_CON01 CRU_REG(0x0184)
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#define CRU_GATE_CON02 CRU_REG(0x0188)
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#define CRU_GATE_CON03 CRU_REG(0x018c)
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#define CRU_GATE_CON04 CRU_REG(0x0190)
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#define CRU_GATE_CON05 CRU_REG(0x0194)
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#define CRU_SOFTRST_CON00 CRU_REG(0x0200)
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#define CRU_SOFTRST_CON01 CRU_REG(0x0204)
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#define CRU_SOFTRST_CON02 CRU_REG(0x0208)
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#define CRU_SOFTRST_CON04 CRU_REG(0x0210)
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#define CRU_MAX_REGISTER CRU_SOFTRST_CON04
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#define CGU_CLK_CPLL 1
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#define CGU_CLK_GPLL 2
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#define CGU_CLK_CPLL_MUX 3
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#define CGU_CLK_GPLL_MUX 4
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#define CGU_PCLK_GPIO0 5
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#define CGU_PCLK_GPIO1 6
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#define CGU_PCLK_GPIO2 7
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#define CGU_PCLK_GPIO3 8
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#define CGU_PCLK_TXPHY_CON 9
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#define CGU_PCLK_EFUSE 10
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#define CGU_PCLK_DSI0 11
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#define CGU_PCLK_DSI1 12
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#define CGU_PCLK_CSI 13
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#define CGU_PCLK_HDMITX 14
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#define CGU_PCLK_RXPHY 15
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#define CGU_PCLK_HDMIRX 16
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#define CGU_PCLK_DPRX 17
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#define CGU_PCLK_GVIHOST 18
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#define CGU_CLK_CFG_DPHY0 19
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#define CGU_CLK_CFG_DPHY1 20
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#define CGU_CLK_TXESC 21
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#define CGU_CLK_DPRX_VID 22
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#define CGU_CLK_IMODET 23
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#define CGU_CLK_HDMIRX_AUD 24
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#define CGU_CLK_HDMIRX_CEC 25
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#define CGU_CLK_RX_READ 26
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#define CGU_SCLK_VOP 27
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#define CGU_PCLK_LOGIC 28
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#define CGU_CLK_GPIO_DB0 29
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#define CGU_CLK_GPIO_DB1 30
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#define CGU_CLK_GPIO_DB2 31
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#define CGU_CLK_GPIO_DB3 32
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#define CGU_CLK_I2S_8CH_SRC 33
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#define CGU_CLK_I2S_8CH_FRAC 34
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#define CGU_MCLK_I2S_8CH 35
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#define CGU_I2S_MCLKOUT 36
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#define CGU_BT1120DEC 37
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#define CGU_SCLK_UART 38
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#define RGU_LOGIC 0
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#define RGU_CRU 1
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#define RGU_REGFILE 2
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#define RGU_I2C2APB 3
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#define RGU_EFUSE 4
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#define RGU_ADAPTER 5
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#define RGU_CLK_RX 6
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#define RGU_BT1120DEC 7
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#define RGU_VOP 8
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#define RGU_GPIO0 9
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#define RGU_GPIO1 10
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#define RGU_GPIO2 11
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#define RGU_GPIO3 12
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#define RGU_GPIO_DB0 13
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#define RGU_GPIO_DB1 14
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#define RGU_GPIO_DB2 15
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#define RGU_GPIO_DB3 16
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#define RGU_RXPHY 17
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#define RGU_HDMIRX 18
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#define RGU_TXPHY_CON 19
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#define RGU_HDMITX 20
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#define RGU_GVIHOST 21
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#define RGU_DSI0 22
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#define RGU_DSI1 23
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#define RGU_CSI 24
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#define RGU_TXDATA 25
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#define RGU_DECODER 26
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#define RGU_ENCODER 27
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#define RGU_HDMIRX_PON 28
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#define RGU_TXBYTEHS 29
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#define RGU_TXESC 30
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unsigned long rk628_clk_get_rate(struct rk628 *rk628, unsigned int id);
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int rk628_clk_set_rate(struct rk628 *rk628, unsigned int id,
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unsigned long rate);
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int rk628_control_assert(struct rk628 *rk628, unsigned long id);
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int rk628_control_deassert(struct rk628 *rk628, unsigned long id);
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void rk628_cru_initialize(struct rk628 *rk628);
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void rk628_clk_mux_testout(struct rk628 *rk628, int id);
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#endif
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