/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen csq@rock-chips.com>
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*/
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#ifndef _RK628_COMBTXPHY_H
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#define _RK628_COMBTXPHY_H
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#define COMBTXPHY_BASE 0x90000
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#define COMBTXPHY_REG(x) ((x) + COMBTXPHY_BASE)
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#define COMBTXPHY_CON0 COMBTXPHY_REG(0x0000)
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#define SW_TX_IDLE_MASK GENMASK(29, 20)
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#define SW_TX_IDLE(x) UPDATE(x, 29, 20)
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#define SW_TX_PD_MASK GENMASK(17, 8)
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#define SW_TX_PD(x) UPDATE(x, 17, 8)
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#define SW_BUS_WIDTH_MASK GENMASK(6, 5)
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#define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
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#define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
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#define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
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#define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
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#define SW_PD_PLL_MASK BIT(4)
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#define SW_PD_PLL BIT(4)
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#define SW_GVI_LVDS_EN_MASK BIT(3)
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#define SW_GVI_LVDS_EN BIT(3)
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#define SW_MIPI_DSI_EN_MASK BIT(2)
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#define SW_MIPI_DSI_EN BIT(2)
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#define SW_MODULEB_EN_MASK BIT(1)
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#define SW_MODULEB_EN BIT(1)
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#define SW_MODULEA_EN_MASK BIT(0)
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#define SW_MODULEA_EN BIT(0)
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#define COMBTXPHY_CON1 COMBTXPHY_REG(0x0004)
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#define COMBTXPHY_CON2 COMBTXPHY_REG(0x0008)
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#define COMBTXPHY_CON3 COMBTXPHY_REG(0x000c)
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#define COMBTXPHY_CON4 COMBTXPHY_REG(0x0010)
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#define COMBTXPHY_CON5 COMBTXPHY_REG(0x0014)
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#define SW_RATE(x) UPDATE(x, 26, 24)
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#define SW_REF_DIV(x) UPDATE(x, 20, 16)
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#define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
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#define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
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#define COMBTXPHY_CON6 COMBTXPHY_REG(0x0018)
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#define COMBTXPHY_CON7 COMBTXPHY_REG(0x001c)
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#define SW_TX_RTERM_MASK GENMASK(22, 20)
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#define SW_TX_RTERM(x) UPDATE(x, 22, 20)
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#define SW_TX_MODE_MASK GENMASK(17, 16)
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#define SW_TX_MODE(x) UPDATE(x, 17, 16)
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#define SW_TX_CTL_CON5_MASK BIT(10)
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#define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10)
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#define SW_TX_CTL_CON4_MASK GENMASK(9, 8)
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#define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8)
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#define COMBTXPHY_CON8 COMBTXPHY_REG(0x0020)
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#define COMBTXPHY_CON9 COMBTXPHY_REG(0x0024)
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#define SW_DSI_FSET_EN_MASK BIT(29)
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#define SW_DSI_FSET_EN BIT(29)
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#define SW_DSI_RCAL_EN_MASK BIT(28)
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#define SW_DSI_RCAL_EN BIT(28)
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#define COMBTXPHY_CON10 COMBTXPHY_REG(0x0028)
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#define TX9_CKDRV_EN BIT(9)
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#define TX8_CKDRV_EN BIT(8)
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#define TX7_CKDRV_EN BIT(7)
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#define TX6_CKDRV_EN BIT(6)
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#define TX5_CKDRV_EN BIT(5)
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#define TX4_CKDRV_EN BIT(4)
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#define TX3_CKDRV_EN BIT(3)
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#define TX2_CKDRV_EN BIT(2)
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#define TX1_CKDRV_EN BIT(1)
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#define TX0_CKDRV_EN BIT(0)
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enum phy_mode {
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PHY_MODE_INVALID,
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PHY_MODE_VIDEO_MIPI,
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PHY_MODE_VIDEO_LVDS,
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PHY_MODE_VIDEO_GVI,
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};
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struct rk628_combtxphy {
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enum phy_mode mode;
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unsigned int flags;
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u8 ref_div;
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u8 fb_div;
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u16 frac_div;
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u8 rate_div;
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u32 bus_width;
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};
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void rk628_txphy_set_mode(struct rk628 *rk628, enum phy_mode mode);
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void rk628_txphy_set_bus_width(struct rk628 *rk628, u32 bus_width);
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u32 rk628_txphy_get_bus_width(struct rk628 *rk628);
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void rk628_txphy_power_on(struct rk628 *rk628);
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void rk628_txphy_power_off(struct rk628 *rk628);
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struct rk628_combtxphy *rk628_txphy_register(struct rk628 *rk628);
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#endif
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