// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#include <linux/delay.h>
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#include "rk628.h"
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#include "rk628_combtxphy.h"
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#include "rk628_cru.h"
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void rk628_txphy_set_bus_width(struct rk628 *rk628, u32 bus_width)
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{
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struct rk628_combtxphy *txphy = rk628->txphy;
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txphy->bus_width = bus_width;
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}
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EXPORT_SYMBOL(rk628_txphy_set_bus_width);
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u32 rk628_txphy_get_bus_width(struct rk628 *rk628)
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{
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struct rk628_combtxphy *txphy = rk628->txphy;
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return txphy->bus_width;
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}
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EXPORT_SYMBOL(rk628_txphy_get_bus_width);
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static void rk628_combtxphy_dsi_power_on(struct rk628 *rk628)
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{
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struct rk628_combtxphy *txphy = rk628->txphy;
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_BUS_WIDTH_MASK |
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SW_GVI_LVDS_EN_MASK |
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SW_MIPI_DSI_EN_MASK,
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SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN);
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if (txphy->flags & COMBTXPHY_MODULEA_EN)
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_MODULEA_EN_MASK,
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SW_MODULEA_EN);
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if (txphy->flags & COMBTXPHY_MODULEB_EN)
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_MODULEB_EN_MASK,
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SW_MODULEB_EN);
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rk628_i2c_write(rk628, COMBTXPHY_CON5, SW_REF_DIV(txphy->ref_div - 1) |
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SW_PLL_FB_DIV(txphy->fb_div) |
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SW_PLL_FRAC_DIV(txphy->frac_div) |
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SW_RATE(txphy->rate_div / 2));
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL, 0);
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usleep_range(100, 200);
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON9, SW_DSI_FSET_EN_MASK |
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SW_DSI_RCAL_EN_MASK, SW_DSI_FSET_EN |
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SW_DSI_RCAL_EN);
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usleep_range(100, 200);
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}
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static void rk628_combtxphy_lvds_power_on(struct rk628 *rk628)
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{
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struct rk628_combtxphy *txphy = rk628->txphy;
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON7, SW_TX_MODE_MASK, SW_TX_MODE(3));
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rk628_i2c_write(rk628, COMBTXPHY_CON10, TX7_CKDRV_EN | TX2_CKDRV_EN);
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_BUS_WIDTH_MASK |
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SW_GVI_LVDS_EN_MASK | SW_MIPI_DSI_EN_MASK,
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SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN);
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if (txphy->flags & COMBTXPHY_MODULEA_EN)
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_MODULEA_EN_MASK,
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SW_MODULEA_EN);
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if (txphy->flags & COMBTXPHY_MODULEB_EN)
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_MODULEB_EN_MASK,
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SW_MODULEB_EN);
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rk628_i2c_write(rk628, COMBTXPHY_CON5, SW_REF_DIV(txphy->ref_div - 1) |
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SW_PLL_FB_DIV(txphy->fb_div) |
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SW_PLL_FRAC_DIV(txphy->frac_div) |
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SW_RATE(txphy->rate_div / 2));
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL | SW_TX_PD_MASK, 0);
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usleep_range(100, 200);
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_TX_IDLE_MASK, 0);
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}
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static void rk628_combtxphy_gvi_power_on(struct rk628 *rk628)
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{
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struct rk628_combtxphy *txphy = rk628->txphy;
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rk628_i2c_write(rk628, COMBTXPHY_CON5, SW_REF_DIV(txphy->ref_div - 1) |
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SW_PLL_FB_DIV(txphy->fb_div) |
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SW_PLL_FRAC_DIV(txphy->frac_div) |
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SW_RATE(txphy->rate_div / 2));
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_BUS_WIDTH_MASK |
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SW_GVI_LVDS_EN_MASK | SW_MIPI_DSI_EN_MASK |
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SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
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SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN |
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SW_MODULEB_EN | SW_MODULEA_EN);
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_PD_PLL | SW_TX_PD_MASK, 0);
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usleep_range(100, 200);
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_TX_IDLE_MASK, 0);
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}
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void rk628_txphy_set_mode(struct rk628 *rk628, enum phy_mode mode)
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{
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unsigned int fvco, frac_rate, fin = 24;
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struct rk628_combtxphy *txphy = rk628->txphy;
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switch (mode) {
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case PHY_MODE_VIDEO_MIPI:
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{
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int bus_width = rk628_txphy_get_bus_width(rk628);
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unsigned int fhsc = bus_width >> 8;
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unsigned int flags = bus_width & 0xff;
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fhsc = fin * (fhsc / fin);
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if (fhsc < 80 || fhsc > 1500)
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return;
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else if (fhsc < 375)
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txphy->rate_div = 4;
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else if (fhsc < 750)
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txphy->rate_div = 2;
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else
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txphy->rate_div = 1;
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txphy->flags = flags;
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fvco = fhsc * 2 * txphy->rate_div;
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txphy->ref_div = 1;
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txphy->fb_div = fvco / 8 / fin;
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frac_rate = fvco - (fin * 8 * txphy->fb_div);
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if (frac_rate) {
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frac_rate <<= 10;
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frac_rate /= fin * 8;
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txphy->frac_div = frac_rate;
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} else {
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txphy->frac_div = 0;
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}
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fvco = fin * (1024 * txphy->fb_div + txphy->frac_div);
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fvco *= 8;
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fvco = DIV_ROUND_UP(fvco, 1024 * txphy->ref_div);
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fhsc = fvco / 2 / txphy->rate_div;
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txphy->bus_width = fhsc;
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break;
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}
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case PHY_MODE_VIDEO_LVDS:
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{
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int bus_width = rk628_txphy_get_bus_width(rk628);
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unsigned int flags = bus_width & 0xff;
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unsigned int rate = (bus_width >> 8) * 7;
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txphy->flags = flags;
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txphy->ref_div = 1;
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txphy->fb_div = 14;
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txphy->frac_div = 0;
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if (rate < 500)
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txphy->rate_div = 4;
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else if (rate < 1000)
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txphy->rate_div = 2;
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else
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txphy->rate_div = 1;
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break;
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}
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case PHY_MODE_VIDEO_GVI:
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{
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unsigned int fhsc = rk628_txphy_get_bus_width(rk628) & 0xfff;
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if (fhsc < 500 || fhsc > 4000)
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return;
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else if (fhsc < 1000)
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txphy->rate_div = 4;
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else if (fhsc < 2000)
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txphy->rate_div = 2;
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else
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txphy->rate_div = 1;
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fvco = fhsc * txphy->rate_div;
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txphy->ref_div = 1;
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txphy->fb_div = fvco / 8 / fin;
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frac_rate = fvco - (fin * 8 * txphy->fb_div);
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if (frac_rate) {
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frac_rate <<= 10;
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frac_rate /= fin * 8;
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txphy->frac_div = frac_rate;
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} else {
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txphy->frac_div = 0;
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}
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fvco = fin * (1024 * txphy->fb_div + txphy->frac_div);
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fvco *= 8;
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fvco /= 1024 * txphy->ref_div;
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fhsc = fvco / txphy->rate_div;
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txphy->bus_width = fhsc;
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break;
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}
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default:
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break;
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}
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txphy->mode = mode;
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}
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EXPORT_SYMBOL(rk628_txphy_set_mode);
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void rk628_txphy_power_on(struct rk628 *rk628)
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{
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struct rk628_combtxphy *txphy = rk628->txphy;
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rk628_control_assert(rk628, RGU_TXPHY_CON);
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udelay(10);
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rk628_control_deassert(rk628, RGU_TXPHY_CON);
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udelay(10);
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_TX_IDLE_MASK | SW_TX_PD_MASK |
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SW_PD_PLL_MASK, SW_TX_IDLE(0x3ff) |
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SW_TX_PD(0x3ff) | SW_PD_PLL);
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switch (txphy->mode) {
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case PHY_MODE_VIDEO_MIPI:
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rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON,
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SW_TXPHY_REFCLK_SEL_MASK,
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SW_TXPHY_REFCLK_SEL(0));
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rk628_combtxphy_dsi_power_on(rk628);
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break;
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case PHY_MODE_VIDEO_LVDS:
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rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON,
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SW_TXPHY_REFCLK_SEL_MASK,
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SW_TXPHY_REFCLK_SEL(1));
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rk628_combtxphy_lvds_power_on(rk628);
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break;
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case PHY_MODE_VIDEO_GVI:
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rk628_i2c_update_bits(rk628, GRF_POST_PROC_CON,
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SW_TXPHY_REFCLK_SEL_MASK,
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SW_TXPHY_REFCLK_SEL(0));
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rk628_combtxphy_gvi_power_on(rk628);
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break;
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default:
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break;
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}
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}
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EXPORT_SYMBOL(rk628_txphy_power_on);
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void rk628_txphy_power_off(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, COMBTXPHY_CON0, SW_TX_IDLE_MASK | SW_TX_PD_MASK |
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SW_PD_PLL_MASK | SW_MODULEB_EN_MASK |
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SW_MODULEA_EN_MASK, SW_TX_IDLE(0x3ff) |
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SW_TX_PD(0x3ff) | SW_PD_PLL);
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}
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EXPORT_SYMBOL(rk628_txphy_power_off);
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struct rk628_combtxphy *rk628_txphy_register(struct rk628 *rk628)
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{
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struct rk628_combtxphy *txphy;
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txphy = devm_kzalloc(rk628->dev, sizeof(*txphy), GFP_KERNEL);
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if (!txphy)
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return NULL;
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rk628->txphy = txphy;
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return txphy;
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}
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EXPORT_SYMBOL(rk628_txphy_register);
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