// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include "rk628.h"
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#include "rk628_combrxphy.h"
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#include "rk628_combtxphy.h"
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#include "rk628_cru.h"
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#include "rk628_csi.h"
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#include "rk628_dsi.h"
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#include "rk628_hdmirx.h"
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static const struct regmap_range rk628_cru_readable_ranges[] = {
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regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
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regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4),
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regmap_reg_range(CRU_MODE_CON00, CRU_MODE_CON00),
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regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21),
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regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05),
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regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04),
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};
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static const struct regmap_access_table rk628_cru_readable_table = {
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.yes_ranges = rk628_cru_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges),
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};
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static const struct regmap_range rk628_combrxphy_readable_ranges[] = {
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regmap_reg_range(COMBRX_REG(0x6600), COMBRX_REG(0x665b)),
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regmap_reg_range(COMBRX_REG(0x66a0), COMBRX_REG(0x66db)),
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regmap_reg_range(COMBRX_REG(0x66f0), COMBRX_REG(0x66ff)),
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regmap_reg_range(COMBRX_REG(0x6700), COMBRX_REG(0x6790)),
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};
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static const struct regmap_access_table rk628_combrxphy_readable_table = {
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.yes_ranges = rk628_combrxphy_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges),
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};
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static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
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regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_SETUP_CTRL),
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regmap_reg_range(HDMI_RX_HDMI_PCB_CTRL, HDMI_RX_HDMI_PCB_CTRL),
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regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERROR_PROTECT),
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regmap_reg_range(HDMI_RX_HDMI_SYNC_CTRL, HDMI_RX_HDMI_CKM_RESULT),
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regmap_reg_range(HDMI_RX_HDMI_RESMPL_CTRL, HDMI_RX_HDMI_RESMPL_CTRL),
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regmap_reg_range(HDMI_VM_CFG_CH2, HDMI_VM_CFG_CH2),
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regmap_reg_range(HDMI_RX_HDCP_CTRL, HDMI_RX_HDCP_SETTINGS),
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regmap_reg_range(HDMI_RX_HDCP_KIDX, HDMI_RX_HDCP_KIDX),
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regmap_reg_range(HDMI_RX_HDCP_DBG, HDMI_RX_HDCP_AN0),
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regmap_reg_range(HDMI_RX_HDCP_STS, HDMI_RX_HDCP_STS),
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regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_HACT_PX),
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regmap_reg_range(HDMI_RX_MD_VCTRL, HDMI_RX_MD_VSC),
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regmap_reg_range(HDMI_RX_MD_VOL, HDMI_RX_MD_VTL),
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regmap_reg_range(HDMI_RX_MD_IL_POL, HDMI_RX_MD_STS),
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regmap_reg_range(HDMI_RX_AUD_CTRL, HDMI_RX_AUD_CTRL),
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regmap_reg_range(HDMI_RX_AUD_PLL_CTRL, HDMI_RX_AUD_PLL_CTRL),
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regmap_reg_range(HDMI_RX_AUD_CLK_CTRL, HDMI_RX_AUD_CLK_CTRL),
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regmap_reg_range(HDMI_RX_AUD_FIFO_CTRL, HDMI_RX_AUD_FIFO_TH),
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regmap_reg_range(HDMI_RX_AUD_CHEXTR_CTRL, HDMI_RX_AUD_PAO_CTRL),
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regmap_reg_range(HDMI_RX_AUD_FIFO_STS, HDMI_RX_AUD_FIFO_STS),
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regmap_reg_range(HDMI_RX_AUDPLL_GEN_CTS, HDMI_RX_AUDPLL_GEN_N),
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regmap_reg_range(HDMI_RX_PDEC_CTRL, HDMI_RX_PDEC_CTRL),
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regmap_reg_range(HDMI_RX_PDEC_AUDIODET_CTRL, HDMI_RX_PDEC_AUDIODET_CTRL),
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regmap_reg_range(HDMI_RX_PDEC_ERR_FILTER, HDMI_RX_PDEC_ASP_CTRL),
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regmap_reg_range(HDMI_RX_PDEC_STS, HDMI_RX_PDEC_STS),
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regmap_reg_range(HDMI_RX_PDEC_GCP_AVMUTE, HDMI_RX_PDEC_GCP_AVMUTE),
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regmap_reg_range(HDMI_RX_PDEC_ACR_CTS, HDMI_RX_PDEC_ACR_N),
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regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_AIF_PB0),
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regmap_reg_range(HDMI_RX_PDEC_AVI_PB, HDMI_RX_PDEC_AVI_PB),
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regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
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regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS2),
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regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA0),
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regmap_reg_range(HDMI_RX_PDEC_ISTS, HDMI_RX_PDEC_IEN),
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regmap_reg_range(HDMI_RX_AUD_FIFO_ISTS, HDMI_RX_AUD_FIFO_IEN),
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regmap_reg_range(HDMI_RX_MD_ISTS, HDMI_RX_MD_IEN),
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regmap_reg_range(HDMI_RX_HDMI_ISTS, HDMI_RX_HDMI_IEN),
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regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
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};
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static const struct regmap_access_table rk628_hdmirx_readable_table = {
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.yes_ranges = rk628_hdmirx_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
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};
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static const struct regmap_range rk628_key_readable_ranges[] = {
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regmap_reg_range(EDID_BASE, EDID_BASE + 0x400),
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};
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static const struct regmap_access_table rk628_key_readable_table = {
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.yes_ranges = rk628_key_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_key_readable_ranges),
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};
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static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
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regmap_reg_range(COMBTXPHY_BASE, COMBTXPHY_CON10),
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};
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static const struct regmap_access_table rk628_combtxphy_readable_table = {
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.yes_ranges = rk628_combtxphy_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
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};
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static const struct regmap_range rk628_csi_readable_ranges[] = {
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regmap_reg_range(CSITX_CONFIG_DONE, CSITX_CSITX_VERSION),
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regmap_reg_range(CSITX_SYS_CTRL0_IMD, CSITX_TIMING_HPW_PADDING_NUM),
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regmap_reg_range(CSITX_VOP_PATH_CTRL, CSITX_VOP_PATH_CTRL),
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regmap_reg_range(CSITX_VOP_PATH_PKT_CTRL, CSITX_VOP_PATH_PKT_CTRL),
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regmap_reg_range(CSITX_CSITX_STATUS0, CSITX_LPDT_DATA_IMD),
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regmap_reg_range(CSITX_DPHY_CTRL, CSITX_DPHY_CTRL),
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};
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static const struct regmap_access_table rk628_csi_readable_table = {
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.yes_ranges = rk628_csi_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_csi_readable_ranges),
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};
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static const struct regmap_range rk628_dsi0_readable_ranges[] = {
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regmap_reg_range(DSI0_BASE, DSI0_BASE + DSI_MAX_REGISTER),
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};
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static const struct regmap_access_table rk628_dsi0_readable_table = {
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.yes_ranges = rk628_dsi0_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_dsi0_readable_ranges),
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};
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static const struct regmap_range rk628_dsi1_readable_ranges[] = {
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regmap_reg_range(DSI1_BASE, DSI1_BASE + DSI_MAX_REGISTER),
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};
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static const struct regmap_access_table rk628_dsi1_readable_table = {
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.yes_ranges = rk628_dsi1_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(rk628_dsi1_readable_ranges),
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};
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static const struct regmap_config rk628_regmap_config[RK628_DEV_MAX] = {
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[RK628_DEV_GRF] = {
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.name = "grf",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = GRF_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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},
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[RK628_DEV_CRU] = {
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.name = "cru",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = CRU_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_cru_readable_table,
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},
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[RK628_DEV_COMBRXPHY] = {
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.name = "combrxphy",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = COMBRX_REG(0x6790),
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_combrxphy_readable_table,
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},
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[RK628_DEV_DSI0] = {
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.name = "dsi0",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = DSI0_BASE + DSI_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_dsi0_readable_table,
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},
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[RK628_DEV_DSI1] = {
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.name = "dsi1",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = DSI1_BASE + DSI_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_dsi1_readable_table,
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},
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[RK628_DEV_HDMIRX] = {
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.name = "hdmirx",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = HDMI_RX_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_hdmirx_readable_table,
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},
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[RK628_DEV_ADAPTER] = {
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.name = "adapter",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = KEY_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_key_readable_table,
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},
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[RK628_DEV_COMBTXPHY] = {
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.name = "combtxphy",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = COMBTXPHY_CON10,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_combtxphy_readable_table,
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},
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[RK628_DEV_CSI] = {
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.name = "csi",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = CSI_MAX_REGISTER,
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.reg_format_endian = REGMAP_ENDIAN_LITTLE,
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.val_format_endian = REGMAP_ENDIAN_LITTLE,
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.rd_table = &rk628_csi_readable_table,
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},
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};
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struct rk628 *rk628_i2c_register(struct i2c_client *client)
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{
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struct rk628 *rk628;
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int i, ret;
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struct device *dev = &client->dev;
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rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
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if (!rk628)
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return NULL;
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rk628->client = client;
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rk628->dev = dev;
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for (i = 0; i < RK628_DEV_MAX; i++) {
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const struct regmap_config *config = &rk628_regmap_config[i];
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if (!config->name)
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continue;
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rk628->regmap[i] = devm_regmap_init_i2c(client, config);
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if (IS_ERR(rk628->regmap[i])) {
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ret = PTR_ERR(rk628->regmap[i]);
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dev_err(dev, "failed to allocate register map %d: %d\n",
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i, ret);
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return NULL;
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}
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}
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return rk628;
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}
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EXPORT_SYMBOL(rk628_i2c_register);
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static void calc_dsp_frm_hst_vst(const struct videomode *src,
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const struct videomode *dst,
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u32 *dsp_frame_hst, u32 *dsp_frame_vst)
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{
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u32 bp_in, bp_out;
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u32 v_scale_ratio;
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u64 t_frm_st;
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u64 t_bp_in, t_bp_out, t_delta, tin;
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u32 src_pixclock, dst_pixclock;
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u32 dsp_htotal, src_htotal, src_vtotal;
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src_pixclock = div_u64(1000000000000llu, src->pixelclock);
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dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
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src_htotal = src->hsync_len + src->hback_porch + src->hactive +
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src->hfront_porch;
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src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
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src->vfront_porch;
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dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
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dst->hfront_porch;
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bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
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src->hsync_len + src->hback_porch;
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bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
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dst->hsync_len + dst->hback_porch;
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t_bp_in = bp_in * src_pixclock;
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t_bp_out = bp_out * dst_pixclock;
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tin = src_vtotal * src_htotal * src_pixclock;
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v_scale_ratio = src->vactive / dst->vactive;
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if (v_scale_ratio <= 2)
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t_delta = 5 * src_htotal * src_pixclock;
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else
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t_delta = 12 * src_htotal * src_pixclock;
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if (t_bp_in + t_delta > t_bp_out)
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t_frm_st = (t_bp_in + t_delta - t_bp_out);
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else
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t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
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do_div(t_frm_st, src_pixclock);
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*dsp_frame_hst = do_div(t_frm_st, src_htotal);
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*dsp_frame_vst = t_frm_st;
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}
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static void rk628_post_process_scaler_init(struct rk628 *rk628,
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const struct videomode *src,
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const struct videomode *dst)
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{
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u32 dsp_frame_hst, dsp_frame_vst;
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u32 scl_hor_mode, scl_ver_mode;
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u32 scl_v_factor, scl_h_factor;
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u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
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u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
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u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
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u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
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u8 hor_down_mode = 0, ver_down_mode = 0;
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dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
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dst->hfront_porch;
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dsp_vtotal = dst->vsync_len + dst->vback_porch + dst->vactive +
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dst->vfront_porch;
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dsp_hs_end = dst->hsync_len;
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dsp_vs_end = dst->vsync_len;
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dsp_hbor_end = dst->hsync_len + dst->hback_porch + dst->hactive;
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dsp_hbor_st = dst->hsync_len + dst->hback_porch;
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dsp_vbor_end = dst->vsync_len + dst->vback_porch + dst->vactive;
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dsp_vbor_st = dst->vsync_len + dst->vback_porch;
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dsp_hact_st = dsp_hbor_st + bor_left;
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dsp_hact_end = dsp_hbor_end - bor_right;
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dsp_vact_st = dsp_vbor_st + bor_up;
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dsp_vact_end = dsp_vbor_end - bor_down;
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calc_dsp_frm_hst_vst(src, dst, &dsp_frame_hst, &dsp_frame_vst);
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dev_dbg(rk628->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
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dsp_frame_vst, dsp_frame_hst);
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if (src->hactive > dst->hactive) {
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scl_hor_mode = 2;
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if (hor_down_mode == 0) {
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if ((src->hactive - 1) / (dst->hactive - 1) > 2)
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scl_h_factor = ((src->hactive - 1) << 14) /
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(dst->hactive - 1);
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else
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scl_h_factor = ((src->hactive - 2) << 14) /
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(dst->hactive - 1);
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} else {
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scl_h_factor = (dst->hactive << 16) /
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(src->hactive - 1);
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}
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dev_dbg(rk628->dev, "horizontal scale down\n");
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} else if (src->hactive == dst->hactive) {
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scl_hor_mode = 0;
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scl_h_factor = 0;
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dev_dbg(rk628->dev, "horizontal no scale\n");
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} else {
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scl_hor_mode = 1;
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scl_h_factor = ((src->hactive - 1) << 16) / (dst->hactive - 1);
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dev_dbg(rk628->dev, "horizontal scale up\n");
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}
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if (src->vactive > dst->vactive) {
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scl_ver_mode = 2;
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if (ver_down_mode == 0) {
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if ((src->vactive - 1) / (dst->vactive - 1) > 2)
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scl_v_factor = ((src->vactive - 1) << 14) /
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(dst->vactive - 1);
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else
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scl_v_factor = ((src->vactive - 2) << 14) /
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(dst->vactive - 1);
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} else {
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scl_v_factor = (dst->vactive << 16) /
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(src->vactive - 1);
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}
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dev_dbg(rk628->dev, "vertical scale down\n");
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} else if (src->vactive == dst->vactive) {
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scl_ver_mode = 0;
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scl_v_factor = 0;
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dev_dbg(rk628->dev, "vertical no scale\n");
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} else {
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scl_ver_mode = 1;
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scl_v_factor = ((src->vactive - 1) << 16) / (dst->vactive - 1);
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dev_dbg(rk628->dev, "vertical scale up\n");
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}
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rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0,
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SW_HRES_MASK, SW_HRES(src->hactive));
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rk628_i2c_write(rk628, GRF_SCALER_CON0,
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SCL_VER_DOWN_MODE(ver_down_mode) |
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SCL_HOR_DOWN_MODE(hor_down_mode) |
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SCL_VER_MODE(scl_ver_mode) |
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SCL_HOR_MODE(scl_hor_mode) |
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SCL_EN(1));
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rk628_i2c_write(rk628, GRF_SCALER_CON1,
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SCL_V_FACTOR(scl_v_factor) |
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SCL_H_FACTOR(scl_h_factor));
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rk628_i2c_write(rk628, GRF_SCALER_CON2,
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DSP_FRAME_VST(dsp_frame_vst) |
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DSP_FRAME_HST(dsp_frame_hst));
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rk628_i2c_write(rk628, GRF_SCALER_CON3,
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DSP_HS_END(dsp_hs_end) |
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DSP_HTOTAL(dsp_htotal));
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rk628_i2c_write(rk628, GRF_SCALER_CON4,
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DSP_HACT_END(dsp_hact_end) |
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DSP_HACT_ST(dsp_hact_st));
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rk628_i2c_write(rk628, GRF_SCALER_CON5,
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DSP_VS_END(dsp_vs_end) |
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DSP_VTOTAL(dsp_vtotal));
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rk628_i2c_write(rk628, GRF_SCALER_CON6,
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DSP_VACT_END(dsp_vact_end) |
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DSP_VACT_ST(dsp_vact_st));
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rk628_i2c_write(rk628, GRF_SCALER_CON7,
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DSP_HBOR_END(dsp_hbor_end) |
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DSP_HBOR_ST(dsp_hbor_st));
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rk628_i2c_write(rk628, GRF_SCALER_CON8,
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DSP_VBOR_END(dsp_vbor_end) |
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DSP_VBOR_ST(dsp_vbor_st));
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}
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void rk628_post_process_en(struct rk628 *rk628,
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struct videomode *src,
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struct videomode *dst,
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u64 *dst_pclk)
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{
|
u64 dst_rate, src_rate;
|
u64 dst_htotal, src_htotal;
|
|
src_rate = src->pixelclock;
|
dst_htotal = dst->hactive + dst->hfront_porch + dst->hsync_len + dst->hback_porch;
|
dst_rate = src_rate * dst->vactive * dst_htotal;
|
src_htotal = src->hactive + src->hfront_porch + src->hsync_len + src->hback_porch;
|
do_div(dst_rate, (src->vactive * src_htotal));
|
dst->pixelclock = dst_rate;
|
*dst_pclk = dst->pixelclock;
|
|
dev_info(rk628->dev, "src %dx%d clock:%lu\n",
|
src->hactive, src->vactive, src->pixelclock);
|
dev_info(rk628->dev, "dst %dx%d clock:%lu\n",
|
dst->hactive, dst->vactive, dst->pixelclock);
|
dst->flags = 0;
|
|
rk628_control_assert(rk628, RGU_DECODER);
|
udelay(10);
|
rk628_control_deassert(rk628, RGU_DECODER);
|
udelay(10);
|
|
rk628_clk_set_rate(rk628, CGU_CLK_RX_READ, src->pixelclock);
|
rk628_control_assert(rk628, RGU_CLK_RX);
|
udelay(10);
|
rk628_control_deassert(rk628, RGU_CLK_RX);
|
udelay(10);
|
|
rk628_clk_set_rate(rk628, CGU_SCLK_VOP, dst->pixelclock);
|
rk628_control_assert(rk628, RGU_VOP);
|
udelay(10);
|
rk628_control_deassert(rk628, RGU_VOP);
|
udelay(10);
|
|
rk628_post_process_scaler_init(rk628, src, dst);
|
}
|
EXPORT_SYMBOL(rk628_post_process_en);
|
|
MODULE_AUTHOR("Shunqing Chen <csq@rock-chips.com>");
|
MODULE_DESCRIPTION("Rockchip RK628 driver");
|
MODULE_LICENSE("GPL");
|
