/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ABI_CSKY_CACHEFLUSH_H
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#define __ABI_CSKY_CACHEFLUSH_H
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/* Keep includes the same across arches. */
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#include <linux/mm.h>
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/*
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* The cache doesn't need to be flushed when TLB entries change when
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* the cache is mapped to physical memory, not virtual memory
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*/
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
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#define PG_dcache_clean PG_arch_1
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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if (test_bit(PG_dcache_clean, &page->flags))
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clear_bit(PG_dcache_clean, &page->flags);
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}
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define flush_icache_range(start, end) cache_wbinv_range(start, end)
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void flush_icache_mm_range(struct mm_struct *mm,
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unsigned long start, unsigned long end);
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void flush_icache_deferred(struct mm_struct *mm);
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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if (vma->vm_flags & VM_EXEC) { \
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dcache_wb_range((unsigned long)dst, \
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(unsigned long)dst + len); \
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flush_icache_mm_range(current->mm, \
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(unsigned long)dst, \
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(unsigned long)dst + len); \
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} \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif /* __ABI_CSKY_CACHEFLUSH_H */
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