From 05f6ba814422a392d59037ebe4412168da0e44db Mon Sep 17 00:00:00 2001
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From: Mark Lam <mark.lam@apple.com>
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Date: Tue, 15 Jun 2021 01:04:01 +0000
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Subject: [PATCH] Add ldp and stp support for FP registers, plus some bug
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fixes. https://bugs.webkit.org/show_bug.cgi?id=226998 rdar://79313717
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Reviewed by Robin Morisset.
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This patch does the following:
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1. Add ldp and stp support for FP registers.
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This simply entails providing wrappers that take FPRegisterID and passing true
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for the V bit to the underlying loadStoreRegisterPairXXX encoding function.
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V is for vector (aka floating point). This will cause bit 26 in the instruction
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to be set indicating that it's loading / storing floating point registers.
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2. Add ARM64 disassembler support ldp and stp for FP registers.
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This includes fixing A64DOpcodeLoadStoreRegisterPair::mask to not exclude the
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FP versions of the instructions.
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3. Add ARM64Assembler query methods for determining if an immediate is encodable
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as the signed 12 bit immediate of ldp and stp instructions.
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4. Fix ldp and stp offset form to take an int instead of an unsigned. The
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immediate it takes is a 12-bit signed int, not unsigned.
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5. In loadStoreRegisterPairXXX encoding functions used by the forms of ldp and stp,
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RELEASE_ASSERT that the passed in immediate is encodable. Unlike ldur / stur,
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there is no form of ldp / stp that takes the offset in a register that can be
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used as a fail over. Hence, if the immediate is not encodable, this is a
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non-recoverable event. The client is responsible for ensuring that the offset
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is encodable.
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6. Added some testmasm tests for testing the offset form (as opposed to PreIndex
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and PostIndex forms) of ldp and stp. We currently only use the offset form
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in our JITs.
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* assembler/ARM64Assembler.h:
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(JSC::ARM64Assembler::isValidLDPImm):
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(JSC::ARM64Assembler::isValidLDPFPImm):
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(JSC::ARM64Assembler::ldp):
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(JSC::ARM64Assembler::ldnp):
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(JSC::ARM64Assembler::isValidSTPImm):
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(JSC::ARM64Assembler::isValidSTPFPImm):
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(JSC::ARM64Assembler::stp):
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(JSC::ARM64Assembler::stnp):
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(JSC::ARM64Assembler::loadStoreRegisterPairPostIndex):
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(JSC::ARM64Assembler::loadStoreRegisterPairPreIndex):
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(JSC::ARM64Assembler::loadStoreRegisterPairOffset):
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(JSC::ARM64Assembler::loadStoreRegisterPairNonTemporal):
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* assembler/AssemblerCommon.h:
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(JSC::isValidSignedImm7):
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* assembler/MacroAssemblerARM64.h:
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(JSC::MacroAssemblerARM64::loadPair64):
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(JSC::MacroAssemblerARM64::storePair64):
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* assembler/testmasm.cpp:
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(JSC::testLoadStorePair64Int64):
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(JSC::testLoadStorePair64Double):
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* disassembler/ARM64/A64DOpcode.cpp:
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(JSC::ARM64Disassembler::A64DOpcodeLoadStoreRegisterPair::format):
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* disassembler/ARM64/A64DOpcode.h:
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Canonical link: https://commits.webkit.org/238801@main
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git-svn-id: https://svn.webkit.org/repository/webkit/trunk@278856 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
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[james.hilliard1@gmail.com: backport from upstream commit
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05f6ba814422a392d59037ebe4412168da0e44db]
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---
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Source/JavaScriptCore/ChangeLog | 61 +++
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.../JavaScriptCore/assembler/ARM64Assembler.h | 104 ++++-
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.../assembler/AssemblerCommon.h | 11 +-
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.../assembler/MacroAssemblerARM64.h | 20 +
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Source/JavaScriptCore/assembler/testmasm.cpp | 437 ++++++++++++++++++
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.../disassembler/ARM64/A64DOpcode.cpp | 8 +-
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.../disassembler/ARM64/A64DOpcode.h | 4 +-
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7 files changed, 630 insertions(+), 15 deletions(-)
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diff --git a/Source/JavaScriptCore/assembler/ARM64Assembler.h b/Source/JavaScriptCore/assembler/ARM64Assembler.h
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index 2cc53c8ccda5..758cbe402779 100644
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--- a/Source/JavaScriptCore/assembler/ARM64Assembler.h
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+++ b/Source/JavaScriptCore/assembler/ARM64Assembler.h
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2012-2020 Apple Inc. All rights reserved.
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+ * Copyright (C) 2012-2021 Apple Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -1114,6 +1114,20 @@ public:
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insn(0x0);
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}
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+ template<int datasize>
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+ ALWAYS_INLINE static bool isValidLDPImm(int immediate)
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+ {
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+ unsigned immedShiftAmount = memPairOffsetShift(false, MEMPAIROPSIZE_INT(datasize));
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+ return isValidSignedImm7(immediate, immedShiftAmount);
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE static bool isValidLDPFPImm(int immediate)
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+ {
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+ unsigned immedShiftAmount = memPairOffsetShift(true, MEMPAIROPSIZE_FP(datasize));
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+ return isValidSignedImm7(immediate, immedShiftAmount);
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+ }
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+
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template<int datasize>
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ALWAYS_INLINE void ldp(RegisterID rt, RegisterID rt2, RegisterID rn, PairPostIndex simm)
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{
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@@ -1129,17 +1143,45 @@ public:
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}
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template<int datasize>
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- ALWAYS_INLINE void ldp(RegisterID rt, RegisterID rt2, RegisterID rn, unsigned pimm = 0)
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+ ALWAYS_INLINE void ldp(RegisterID rt, RegisterID rt2, RegisterID rn, int simm = 0)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_INT(datasize), false, MemOp_LOAD, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void ldnp(RegisterID rt, RegisterID rt2, RegisterID rn, int simm = 0)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairNonTemporal(MEMPAIROPSIZE_INT(datasize), false, MemOp_LOAD, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void ldp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, PairPostIndex simm)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairPostIndex(MEMPAIROPSIZE_FP(datasize), true, MemOp_LOAD, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void ldp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, PairPreIndex simm)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairPreIndex(MEMPAIROPSIZE_FP(datasize), true, MemOp_LOAD, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void ldp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, int simm = 0)
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{
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CHECK_DATASIZE();
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- insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_INT(datasize), false, MemOp_LOAD, pimm, rn, rt, rt2));
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+ insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_FP(datasize), true, MemOp_LOAD, simm, rn, rt, rt2));
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}
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template<int datasize>
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- ALWAYS_INLINE void ldnp(RegisterID rt, RegisterID rt2, RegisterID rn, unsigned pimm = 0)
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+ ALWAYS_INLINE void ldnp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, int simm = 0)
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{
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CHECK_DATASIZE();
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- insn(loadStoreRegisterPairNonTemporal(MEMPAIROPSIZE_INT(datasize), false, MemOp_LOAD, pimm, rn, rt, rt2));
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+ insn(loadStoreRegisterPairNonTemporal(MEMPAIROPSIZE_FP(datasize), true, MemOp_LOAD, simm, rn, rt, rt2));
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}
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template<int datasize>
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@@ -1743,6 +1785,18 @@ public:
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smaddl(rd, rn, rm, ARM64Registers::zr);
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}
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+ template<int datasize>
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+ ALWAYS_INLINE static bool isValidSTPImm(int immediate)
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+ {
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+ return isValidLDPImm<datasize>(immediate);
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE static bool isValidSTPFPImm(int immediate)
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+ {
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+ return isValidLDPFPImm<datasize>(immediate);
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+ }
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+
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template<int datasize>
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ALWAYS_INLINE void stp(RegisterID rt, RegisterID rt2, RegisterID rn, PairPostIndex simm)
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{
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@@ -1758,17 +1812,45 @@ public:
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}
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template<int datasize>
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- ALWAYS_INLINE void stp(RegisterID rt, RegisterID rt2, RegisterID rn, unsigned pimm = 0)
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+ ALWAYS_INLINE void stp(RegisterID rt, RegisterID rt2, RegisterID rn, int simm = 0)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_INT(datasize), false, MemOp_STORE, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void stnp(RegisterID rt, RegisterID rt2, RegisterID rn, int simm = 0)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairNonTemporal(MEMPAIROPSIZE_INT(datasize), false, MemOp_STORE, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void stp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, PairPostIndex simm)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairPostIndex(MEMPAIROPSIZE_FP(datasize), true, MemOp_STORE, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void stp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, PairPreIndex simm)
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+ {
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+ CHECK_DATASIZE();
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+ insn(loadStoreRegisterPairPreIndex(MEMPAIROPSIZE_FP(datasize), true, MemOp_STORE, simm, rn, rt, rt2));
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+ }
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+
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+ template<int datasize>
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+ ALWAYS_INLINE void stp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, int simm = 0)
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{
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CHECK_DATASIZE();
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- insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_INT(datasize), false, MemOp_STORE, pimm, rn, rt, rt2));
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+ insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_FP(datasize), true, MemOp_STORE, simm, rn, rt, rt2));
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}
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template<int datasize>
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- ALWAYS_INLINE void stnp(RegisterID rt, RegisterID rt2, RegisterID rn, unsigned pimm = 0)
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+ ALWAYS_INLINE void stnp(FPRegisterID rt, FPRegisterID rt2, RegisterID rn, int simm = 0)
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{
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CHECK_DATASIZE();
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- insn(loadStoreRegisterPairNonTemporal(MEMPAIROPSIZE_INT(datasize), false, MemOp_STORE, pimm, rn, rt, rt2));
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+ insn(loadStoreRegisterPairNonTemporal(MEMPAIROPSIZE_FP(datasize), true, MemOp_STORE, simm, rn, rt, rt2));
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}
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template<int datasize>
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@@ -3544,6 +3626,7 @@ protected:
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ASSERT(opc == (opc & 1)); // Only load or store, load signed 64 is handled via size.
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ASSERT(V || (size != MemPairOp_LoadSigned_32) || (opc == MemOp_LOAD)); // There isn't an integer store signed.
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unsigned immedShiftAmount = memPairOffsetShift(V, size);
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+ RELEASE_ASSERT(isValidSignedImm7(immediate, immedShiftAmount));
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int imm7 = immediate >> immedShiftAmount;
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ASSERT((imm7 << immedShiftAmount) == immediate && isInt<7>(imm7));
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return (0x28800000 | size << 30 | V << 26 | opc << 22 | (imm7 & 0x7f) << 15 | rt2 << 10 | xOrSp(rn) << 5 | rt);
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@@ -3575,6 +3658,7 @@ protected:
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ASSERT(opc == (opc & 1)); // Only load or store, load signed 64 is handled via size.
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ASSERT(V || (size != MemPairOp_LoadSigned_32) || (opc == MemOp_LOAD)); // There isn't an integer store signed.
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unsigned immedShiftAmount = memPairOffsetShift(V, size);
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+ RELEASE_ASSERT(isValidSignedImm7(immediate, immedShiftAmount));
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int imm7 = immediate >> immedShiftAmount;
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ASSERT((imm7 << immedShiftAmount) == immediate && isInt<7>(imm7));
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return (0x29800000 | size << 30 | V << 26 | opc << 22 | (imm7 & 0x7f) << 15 | rt2 << 10 | xOrSp(rn) << 5 | rt);
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@@ -3592,6 +3676,7 @@ protected:
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ASSERT(opc == (opc & 1)); // Only load or store, load signed 64 is handled via size.
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ASSERT(V || (size != MemPairOp_LoadSigned_32) || (opc == MemOp_LOAD)); // There isn't an integer store signed.
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unsigned immedShiftAmount = memPairOffsetShift(V, size);
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+ RELEASE_ASSERT(isValidSignedImm7(immediate, immedShiftAmount));
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int imm7 = immediate >> immedShiftAmount;
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ASSERT((imm7 << immedShiftAmount) == immediate && isInt<7>(imm7));
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return (0x29000000 | size << 30 | V << 26 | opc << 22 | (imm7 & 0x7f) << 15 | rt2 << 10 | xOrSp(rn) << 5 | rt);
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@@ -3609,6 +3694,7 @@ protected:
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ASSERT(opc == (opc & 1)); // Only load or store, load signed 64 is handled via size.
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ASSERT(V || (size != MemPairOp_LoadSigned_32) || (opc == MemOp_LOAD)); // There isn't an integer store signed.
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unsigned immedShiftAmount = memPairOffsetShift(V, size);
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+ RELEASE_ASSERT(isValidSignedImm7(immediate, immedShiftAmount));
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int imm7 = immediate >> immedShiftAmount;
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ASSERT((imm7 << immedShiftAmount) == immediate && isInt<7>(imm7));
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return (0x28000000 | size << 30 | V << 26 | opc << 22 | (imm7 & 0x7f) << 15 | rt2 << 10 | xOrSp(rn) << 5 | rt);
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diff --git a/Source/JavaScriptCore/assembler/AssemblerCommon.h b/Source/JavaScriptCore/assembler/AssemblerCommon.h
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index a594823d6a4d..2e50ffdbc82a 100644
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--- a/Source/JavaScriptCore/assembler/AssemblerCommon.h
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+++ b/Source/JavaScriptCore/assembler/AssemblerCommon.h
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2012-2019 Apple Inc. All rights reserved.
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+ * Copyright (C) 2012-2021 Apple Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -74,6 +74,15 @@ ALWAYS_INLINE bool isValidSignedImm9(int32_t value)
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return isInt9(value);
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}
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+ALWAYS_INLINE bool isValidSignedImm7(int32_t value, int alignmentShiftAmount)
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+{
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+ constexpr int32_t disallowedHighBits = 32 - 7;
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+ int32_t shiftedValue = value >> alignmentShiftAmount;
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+ bool fitsIn7Bits = shiftedValue == ((shiftedValue << disallowedHighBits) >> disallowedHighBits);
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+ bool hasCorrectAlignment = value == (shiftedValue << alignmentShiftAmount);
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+ return fitsIn7Bits && hasCorrectAlignment;
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+}
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+
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class ARM64LogicalImmediate {
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public:
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static ARM64LogicalImmediate create32(uint32_t value)
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diff --git a/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h b/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h
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index f86aec1c5400..14e477fde3b8 100644
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--- a/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h
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+++ b/Source/JavaScriptCore/assembler/MacroAssemblerARM64.h
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@@ -1244,6 +1244,16 @@ public:
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m_assembler.ldnp<64>(dest1, dest2, src, offset.m_value);
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}
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+ void loadPair64(RegisterID src, FPRegisterID dest1, FPRegisterID dest2)
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+ {
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+ loadPair64(src, TrustedImm32(0), dest1, dest2);
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+ }
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+
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+ void loadPair64(RegisterID src, TrustedImm32 offset, FPRegisterID dest1, FPRegisterID dest2)
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+ {
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+ m_assembler.ldp<64>(dest1, dest2, src, offset.m_value);
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+ }
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+
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void abortWithReason(AbortReason reason)
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{
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// It is safe to use dataTempRegister directly since this is a crashing JIT Assert.
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@@ -1568,6 +1578,16 @@ public:
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m_assembler.stnp<64>(src1, src2, dest, offset.m_value);
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}
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+ void storePair64(FPRegisterID src1, FPRegisterID src2, RegisterID dest)
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+ {
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+ storePair64(src1, src2, dest, TrustedImm32(0));
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+ }
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+
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+ void storePair64(FPRegisterID src1, FPRegisterID src2, RegisterID dest, TrustedImm32 offset)
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+ {
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+ m_assembler.stp<64>(src1, src2, dest, offset.m_value);
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+ }
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+
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void store32(RegisterID src, ImplicitAddress address)
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{
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if (tryStoreWithOffset<32>(src, address.base, address.offset))
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diff --git a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp
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index 247c79dcb428..dfe09b671470 100644
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--- a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp
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+++ b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.cpp
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2012, 2016 Apple Inc. All rights reserved.
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+ * Copyright (C) 2012-2021 Apple Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -72,6 +72,8 @@ static const OpcodeGroupInitializer opcodeGroupList[] = {
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OPCODE_GROUP_ENTRY(0x0a, A64DOpcodeLogicalShiftedRegister),
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OPCODE_GROUP_ENTRY(0x0b, A64DOpcodeAddSubtractExtendedRegister),
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OPCODE_GROUP_ENTRY(0x0b, A64DOpcodeAddSubtractShiftedRegister),
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+ OPCODE_GROUP_ENTRY(0x0c, A64DOpcodeLoadStoreRegisterPair),
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+ OPCODE_GROUP_ENTRY(0x0d, A64DOpcodeLoadStoreRegisterPair),
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OPCODE_GROUP_ENTRY(0x11, A64DOpcodeAddSubtractImmediate),
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OPCODE_GROUP_ENTRY(0x12, A64DOpcodeMoveWide),
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OPCODE_GROUP_ENTRY(0x12, A64DOpcodeLogicalImmediate),
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@@ -1363,9 +1365,9 @@ const char* A64DOpcodeLoadStoreRegisterPair::format()
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appendInstructionName(thisOpName);
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unsigned offsetShift;
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if (vBit()) {
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- appendFPRegisterName(rt(), size());
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+ appendFPRegisterName(rt(), size() + 2);
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appendSeparator();
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- appendFPRegisterName(rt2(), size());
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+ appendFPRegisterName(rt2(), size() + 2);
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offsetShift = size() + 2;
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} else {
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if (!lBit())
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diff --git a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h
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index e071babb8e01..fd9db7cae58e 100644
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--- a/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h
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+++ b/Source/JavaScriptCore/disassembler/ARM64/A64DOpcode.h
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2012-2019 Apple Inc. All rights reserved.
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+ * Copyright (C) 2012-2021 Apple Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
* modification, are permitted provided that the following conditions
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@@ -787,7 +787,7 @@ public:
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class A64DOpcodeLoadStoreRegisterPair : public A64DOpcodeLoadStore {
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public:
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- static constexpr uint32_t mask = 0x3a000000;
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+ static constexpr uint32_t mask = 0x38000000;
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static constexpr uint32_t pattern = 0x28000000;
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DEFINE_STATIC_FORMAT(A64DOpcodeLoadStoreRegisterPair, thisObj);
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--
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2.25.1
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