/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
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#define __DAL_TIMING_GENERATOR_TYPES_H__
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#include "hw_shared.h"
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struct dc_bios;
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/* Contains CRTC vertical/horizontal pixel counters */
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struct crtc_position {
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int32_t vertical_count;
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int32_t horizontal_count;
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int32_t nominal_vcount;
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};
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struct dcp_gsl_params {
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int gsl_group;
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int gsl_master;
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};
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struct gsl_params {
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int gsl0_en;
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int gsl1_en;
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int gsl2_en;
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int gsl_master_en;
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int gsl_master_mode;
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int master_update_lock_gsl_en;
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int gsl_window_start_x;
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int gsl_window_end_x;
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int gsl_window_start_y;
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int gsl_window_end_y;
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};
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/* define the structure of Dynamic Refresh Mode */
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struct drr_params {
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uint32_t vertical_total_min;
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uint32_t vertical_total_max;
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uint32_t vertical_total_mid;
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uint32_t vertical_total_mid_frame_num;
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bool immediate_flip;
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};
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#define LEFT_EYE_3D_PRIMARY_SURFACE 1
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#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
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enum crtc_state {
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CRTC_STATE_VBLANK = 0,
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CRTC_STATE_VACTIVE
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};
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struct vupdate_keepout_params {
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int start_offset;
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int end_offset;
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int enable;
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};
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struct crtc_stereo_flags {
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uint8_t PROGRAM_STEREO : 1;
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uint8_t PROGRAM_POLARITY : 1;
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uint8_t RIGHT_EYE_POLARITY : 1;
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uint8_t FRAME_PACKED : 1;
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uint8_t DISABLE_STEREO_DP_SYNC : 1;
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};
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enum crc_selection {
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/* Order must match values expected by hardware */
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UNION_WINDOW_A_B = 0,
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UNION_WINDOW_A_NOT_B,
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UNION_WINDOW_NOT_A_B,
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UNION_WINDOW_NOT_A_NOT_B,
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INTERSECT_WINDOW_A_B,
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INTERSECT_WINDOW_A_NOT_B,
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INTERSECT_WINDOW_NOT_A_B,
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INTERSECT_WINDOW_NOT_A_NOT_B,
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};
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#ifdef CONFIG_DRM_AMD_DC_DCN3_0
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enum otg_out_mux_dest {
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OUT_MUX_DIO = 0,
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};
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#endif
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enum h_timing_div_mode {
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H_TIMING_NO_DIV,
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H_TIMING_DIV_BY2,
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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H_TIMING_RESERVED,
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H_TIMING_DIV_BY4,
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#endif
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};
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struct crc_params {
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/* Regions used to calculate CRC*/
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uint16_t windowa_x_start;
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uint16_t windowa_x_end;
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uint16_t windowa_y_start;
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uint16_t windowa_y_end;
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uint16_t windowb_x_start;
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uint16_t windowb_x_end;
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uint16_t windowb_y_start;
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uint16_t windowb_y_end;
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enum crc_selection selection;
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uint8_t dsc_mode;
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uint8_t odm_mode;
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bool continuous_mode;
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bool enable;
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};
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struct timing_generator {
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const struct timing_generator_funcs *funcs;
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struct dc_bios *bp;
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struct dc_context *ctx;
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int inst;
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};
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struct dc_crtc_timing;
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struct drr_params;
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struct timing_generator_funcs {
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bool (*validate_timing)(struct timing_generator *tg,
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const struct dc_crtc_timing *timing);
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void (*program_timing)(struct timing_generator *tg,
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const struct dc_crtc_timing *timing,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width,
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const enum signal_type signal,
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bool use_vbios
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);
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void (*setup_vertical_interrupt0)(
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struct timing_generator *optc,
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uint32_t start_line,
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uint32_t end_line);
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void (*setup_vertical_interrupt1)(
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struct timing_generator *optc,
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uint32_t start_line);
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void (*setup_vertical_interrupt2)(
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struct timing_generator *optc,
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uint32_t start_line);
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bool (*enable_crtc)(struct timing_generator *tg);
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bool (*disable_crtc)(struct timing_generator *tg);
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bool (*is_counter_moving)(struct timing_generator *tg);
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void (*get_position)(struct timing_generator *tg,
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struct crtc_position *position);
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uint32_t (*get_frame_count)(struct timing_generator *tg);
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void (*get_scanoutpos)(
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struct timing_generator *tg,
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uint32_t *v_blank_start,
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uint32_t *v_blank_end,
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uint32_t *h_position,
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uint32_t *v_position);
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bool (*get_otg_active_size)(struct timing_generator *optc,
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uint32_t *otg_active_width,
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uint32_t *otg_active_height);
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bool (*is_matching_timing)(struct timing_generator *tg,
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const struct dc_crtc_timing *otg_timing);
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void (*set_early_control)(struct timing_generator *tg,
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uint32_t early_cntl);
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void (*wait_for_state)(struct timing_generator *tg,
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enum crtc_state state);
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void (*set_blank)(struct timing_generator *tg,
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bool enable_blanking);
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bool (*is_blanked)(struct timing_generator *tg);
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void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
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void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
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void (*set_colors)(struct timing_generator *tg,
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const struct tg_color *blank_color,
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const struct tg_color *overscan_color);
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void (*disable_vga)(struct timing_generator *tg);
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bool (*did_triggered_reset_occur)(struct timing_generator *tg);
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void (*setup_global_swap_lock)(struct timing_generator *tg,
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const struct dcp_gsl_params *gsl_params);
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void (*unlock)(struct timing_generator *tg);
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void (*lock)(struct timing_generator *tg);
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void (*lock_doublebuffer_disable)(struct timing_generator *tg);
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void (*lock_doublebuffer_enable)(struct timing_generator *tg);
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void(*triplebuffer_unlock)(struct timing_generator *tg);
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void(*triplebuffer_lock)(struct timing_generator *tg);
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void (*enable_reset_trigger)(struct timing_generator *tg,
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int source_tg_inst);
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void (*enable_crtc_reset)(struct timing_generator *tg,
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int source_tg_inst,
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struct crtc_trigger_info *crtc_tp);
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void (*disable_reset_trigger)(struct timing_generator *tg);
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void (*tear_down_global_swap_lock)(struct timing_generator *tg);
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void (*enable_advanced_request)(struct timing_generator *tg,
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bool enable, const struct dc_crtc_timing *timing);
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void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
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void (*set_static_screen_control)(struct timing_generator *tg,
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uint32_t event_triggers,
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uint32_t num_frames);
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void (*set_test_pattern)(
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struct timing_generator *tg,
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enum controller_dp_test_pattern test_pattern,
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enum dc_color_depth color_depth);
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bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
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void (*program_global_sync)(struct timing_generator *tg,
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int vready_offset,
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int vstartup_start,
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int vupdate_offset,
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int vupdate_width);
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void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
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void (*program_stereo)(struct timing_generator *tg,
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const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
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bool (*is_stereo_left_eye)(struct timing_generator *tg);
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void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
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void (*tg_init)(struct timing_generator *tg);
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bool (*is_tg_enabled)(struct timing_generator *tg);
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bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
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void (*clear_optc_underflow)(struct timing_generator *tg);
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void (*set_dwb_source)(struct timing_generator *optc,
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uint32_t dwb_pipe_inst);
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void (*get_optc_source)(struct timing_generator *optc,
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uint32_t *num_of_input_segments,
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uint32_t *seg0_src_sel,
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uint32_t *seg1_src_sel);
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/**
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* Configure CRCs for the given timing generator. Return false if TG is
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* not on.
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*/
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bool (*configure_crc)(struct timing_generator *tg,
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const struct crc_params *params);
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/**
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* Get CRCs for the given timing generator. Return false if CRCs are
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* not enabled (via configure_crc).
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*/
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bool (*get_crc)(struct timing_generator *tg,
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uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
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void (*program_manual_trigger)(struct timing_generator *optc);
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void (*setup_manual_trigger)(struct timing_generator *optc);
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bool (*get_hw_timing)(struct timing_generator *optc,
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struct dc_crtc_timing *hw_crtc_timing);
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void (*set_vtg_params)(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing);
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void (*set_dsc_config)(struct timing_generator *optc,
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enum optc_dsc_mode dsc_mode,
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uint32_t dsc_bytes_per_pixel,
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uint32_t dsc_slice_width);
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void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
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void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
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struct dc_crtc_timing *timing);
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void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
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void (*set_gsl_source_select)(struct timing_generator *optc,
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int group_idx,
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uint32_t gsl_ready_signal);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
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void (*set_vrr_m_const)(struct timing_generator *optc,
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double vtotal_avg);
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void (*set_drr_trigger_window)(struct timing_generator *optc,
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uint32_t window_start, uint32_t window_end);
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void (*set_vtotal_change_limit)(struct timing_generator *optc,
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uint32_t limit);
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#endif
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};
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#endif
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