/* Copyright 2012-17 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_DWBC_H__
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#define __DC_DWBC_H__
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#include "dal_types.h"
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#include "dc_hw_types.h"
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#define DWB_SW_V2 1
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#define DWB_MCIF_BUF_COUNT 4
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/* forward declaration of mcif_wb struct */
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struct mcif_wb;
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enum dwb_sw_version {
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dwb_ver_1_0 = 1,
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dwb_ver_2_0 = 2,
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};
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enum dwb_source {
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dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */
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dwb_src_blnd, /* for DCE7x/9x */
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dwb_src_fmt, /* for DCE7x/9x */
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dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
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dwb_src_otg1, /* for DCN1.x/DCN2.x */
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dwb_src_otg2, /* for DCN1.x/DCN2.x */
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dwb_src_otg3, /* for DCN1.x/DCN2.x */
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};
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/* DCN1.x, DCN2.x support 2 pipes */
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enum dwb_pipe {
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dwb_pipe0 = 0,
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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dwb_pipe1,
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#endif
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dwb_pipe_max_num,
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};
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enum dwb_frame_capture_enable {
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DWB_FRAME_CAPTURE_DISABLE = 0,
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DWB_FRAME_CAPTURE_ENABLE = 1,
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};
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enum wbscl_coef_filter_type_sel {
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WBSCL_COEF_LUMA_VERT_FILTER = 0,
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WBSCL_COEF_CHROMA_VERT_FILTER = 1,
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WBSCL_COEF_LUMA_HORZ_FILTER = 2,
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WBSCL_COEF_CHROMA_HORZ_FILTER = 3
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};
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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enum dwb_boundary_mode {
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DWBSCL_BOUNDARY_MODE_EDGE = 0,
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DWBSCL_BOUNDARY_MODE_BLACK = 1
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};
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#endif
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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enum dwb_output_csc_mode {
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DWB_OUTPUT_CSC_DISABLE = 0,
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DWB_OUTPUT_CSC_COEF_A = 1,
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DWB_OUTPUT_CSC_COEF_B = 2
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};
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enum dwb_ogam_lut_mode {
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DWB_OGAM_MODE_BYPASS,
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DWB_OGAM_RAMA_LUT,
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DWB_OGAM_RAMB_LUT
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};
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enum dwb_color_volume {
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DWB_SRGB_BT709 = 0, //SDR
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DWB_PQ = 1, //HDR
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DWB_HLG = 2, //HDR
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};
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enum dwb_color_space {
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DWB_SRGB = 0, //SDR
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DWB_BT709 = 1, //SDR
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DWB_BT2020 = 2, //HDR
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};
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struct dwb_efc_hdr_metadata {
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/*display chromaticities and white point in units of 0.00001 */
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unsigned int chromaticity_green_x;
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unsigned int chromaticity_green_y;
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unsigned int chromaticity_blue_x;
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unsigned int chromaticity_blue_y;
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unsigned int chromaticity_red_x;
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unsigned int chromaticity_red_y;
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unsigned int chromaticity_white_point_x;
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unsigned int chromaticity_white_point_y;
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/*in units of candelas per square meter */
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unsigned int min_luminance;
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unsigned int max_luminance;
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/*in units of nits */
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unsigned int maximum_content_light_level;
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unsigned int maximum_frame_average_light_level;
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};
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struct dwb_efc_display_settings {
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unsigned int inputColorVolume;
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unsigned int inputColorSpace;
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unsigned int inputBitDepthMinus8;
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struct dwb_efc_hdr_metadata hdr_metadata;
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unsigned int dwbOutputBlack; // 0 - Normal, 1 - Output Black
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};
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#endif
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struct dwb_warmup_params {
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bool warmup_en; /* false: normal mode, true: enable pattern generator */
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bool warmup_mode; /* false: 420, true: 444 */
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bool warmup_depth; /* false: 8bit, true: 10bit */
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int warmup_data; /* Data to be sent by pattern generator (same for each pixel component) */
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int warmup_width; /* Pattern width (pixels) */
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int warmup_height; /* Pattern height (lines) */
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};
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struct dwb_caps {
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enum dce_version hw_version; /* DCN engine version. */
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enum dwb_sw_version sw_version; /* DWB sw implementation version. */
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unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */
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unsigned int adapter_id;
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unsigned int num_pipes; /* number of DWB pipes */
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struct {
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unsigned int support_dwb :1;
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unsigned int support_ogam :1;
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unsigned int support_wbscl :1;
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unsigned int support_ocsc :1;
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unsigned int support_stereo :1;
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} caps;
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unsigned int reserved2[9]; /* Reserved for future use, MUST BE 0. */
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};
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struct dwbc {
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const struct dwbc_funcs *funcs;
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struct dc_context *ctx;
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int inst;
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struct mcif_wb *mcif;
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bool status;
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int inputSrcSelect;
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bool dwb_output_black;
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enum dc_transfer_func_predefined tf;
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enum dc_color_space output_color_space;
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bool dwb_is_efc_transition;
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bool dwb_is_drc;
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int wb_src_plane_inst;/*hubp, mpcc, inst*/
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bool update_privacymask;
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uint32_t mask_id;
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int otg_inst;
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bool mvc_cfg;
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};
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struct dwbc_funcs {
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bool (*get_caps)(
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struct dwbc *dwbc,
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struct dwb_caps *caps);
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bool (*enable)(
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struct dwbc *dwbc,
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struct dc_dwb_params *params);
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bool (*disable)(struct dwbc *dwbc);
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bool (*update)(
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struct dwbc *dwbc,
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struct dc_dwb_params *params);
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bool (*is_enabled)(
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struct dwbc *dwbc);
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void (*set_stereo)(
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struct dwbc *dwbc,
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struct dwb_stereo_params *stereo_params);
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void (*set_new_content)(
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struct dwbc *dwbc,
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bool is_new_content);
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void (*set_warmup)(
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struct dwbc *dwbc,
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struct dwb_warmup_params *warmup_params);
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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void (*dwb_program_output_csc)(
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struct dwbc *dwbc,
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enum dc_color_space color_space,
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enum dwb_output_csc_mode mode);
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bool (*dwb_ogam_set_output_transfer_func)(
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struct dwbc *dwbc,
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const struct dc_transfer_func *in_transfer_func_dwb_ogam);
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void (*get_privacy_mask)(
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struct dwbc *dwbc, uint32_t *mask_id);
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void (*set_privacy_mask)(
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struct dwbc *dwbc, uint32_t mask_id);
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//TODO: merge with output_transfer_func?
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bool (*dwb_ogam_set_input_transfer_func)(
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struct dwbc *dwbc,
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const struct dc_transfer_func *in_transfer_func_dwb_ogam);
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#endif
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bool (*get_dwb_status)(
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struct dwbc *dwbc);
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void (*dwb_set_scaler)(
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struct dwbc *dwbc,
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struct dc_dwb_params *params);
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};
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#endif
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