/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dm_services.h"
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#include "dc.h"
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#include "core_types.h"
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#include "dce112_hw_sequencer.h"
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#include "dce110/dce110_hw_sequencer.h"
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/* include DCE11.2 register header files */
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#include "dce/dce_11_2_d.h"
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#include "dce/dce_11_2_sh_mask.h"
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struct dce112_hw_seq_reg_offsets {
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uint32_t crtc;
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};
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static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
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{
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.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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},
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{
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.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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},
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{
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.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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},
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{
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.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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},
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{
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.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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},
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{
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.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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}
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};
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#define HW_REG_CRTC(reg, id)\
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(reg + reg_offsets[id].crtc)
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/*******************************************************************************
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* Private definitions
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******************************************************************************/
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static void dce112_init_pte(struct dc_context *ctx)
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{
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uint32_t addr;
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uint32_t value = 0;
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uint32_t chunk_int = 0;
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uint32_t chunk_mul = 0;
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addr = mmDVMM_PTE_REQ;
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value = dm_read_reg(ctx, addr);
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chunk_int = get_reg_field_value(
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value,
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DVMM_PTE_REQ,
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HFLIP_PTEREQ_PER_CHUNK_INT);
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chunk_mul = get_reg_field_value(
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value,
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DVMM_PTE_REQ,
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HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
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if (chunk_int != 0x4 || chunk_mul != 0x4) {
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set_reg_field_value(
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value,
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255,
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DVMM_PTE_REQ,
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MAX_PTEREQ_TO_ISSUE);
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set_reg_field_value(
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value,
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4,
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DVMM_PTE_REQ,
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HFLIP_PTEREQ_PER_CHUNK_INT);
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set_reg_field_value(
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value,
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4,
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DVMM_PTE_REQ,
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HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
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dm_write_reg(ctx, addr, value);
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}
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}
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static bool dce112_enable_display_power_gating(
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struct dc *dc,
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uint8_t controller_id,
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struct dc_bios *dcb,
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enum pipe_gating_control power_gating)
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{
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enum bp_result bp_result = BP_RESULT_OK;
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enum bp_pipe_control_action cntl;
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struct dc_context *ctx = dc->ctx;
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if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
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return true;
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if (power_gating == PIPE_GATING_CONTROL_INIT)
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cntl = ASIC_PIPE_INIT;
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else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
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cntl = ASIC_PIPE_ENABLE;
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else
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cntl = ASIC_PIPE_DISABLE;
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if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
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bp_result = dcb->funcs->enable_disp_power_gating(
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dcb, controller_id + 1, cntl);
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/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
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* by default when command table is called
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*/
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dm_write_reg(ctx,
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HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
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0);
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}
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if (power_gating != PIPE_GATING_CONTROL_ENABLE)
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dce112_init_pte(ctx);
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if (bp_result == BP_RESULT_OK)
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return true;
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else
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return false;
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}
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void dce112_hw_sequencer_construct(struct dc *dc)
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{
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/* All registers used by dce11.2 match those in dce11 in offset and
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* structure
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*/
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dce110_hw_sequencer_construct(dc);
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dc->hwseq->funcs.enable_display_power_gating = dce112_enable_display_power_gating;
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}
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