/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTX CPT driver
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*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __OTX_CPT_ALGS_H
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#define __OTX_CPT_ALGS_H
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#include <crypto/hash.h>
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#include "otx_cpt_common.h"
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#define OTX_CPT_MAX_ENC_KEY_SIZE 32
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#define OTX_CPT_MAX_HASH_KEY_SIZE 64
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#define OTX_CPT_MAX_KEY_SIZE (OTX_CPT_MAX_ENC_KEY_SIZE + \
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OTX_CPT_MAX_HASH_KEY_SIZE)
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enum otx_cpt_request_type {
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OTX_CPT_ENC_DEC_REQ = 0x1,
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OTX_CPT_AEAD_ENC_DEC_REQ = 0x2,
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OTX_CPT_AEAD_ENC_DEC_NULL_REQ = 0x3,
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OTX_CPT_PASSTHROUGH_REQ = 0x4
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};
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enum otx_cpt_major_opcodes {
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OTX_CPT_MAJOR_OP_MISC = 0x01,
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OTX_CPT_MAJOR_OP_FC = 0x33,
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OTX_CPT_MAJOR_OP_HMAC = 0x35,
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};
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enum otx_cpt_req_type {
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OTX_CPT_AE_CORE_REQ,
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OTX_CPT_SE_CORE_REQ
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};
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enum otx_cpt_cipher_type {
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OTX_CPT_CIPHER_NULL = 0x0,
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OTX_CPT_DES3_CBC = 0x1,
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OTX_CPT_DES3_ECB = 0x2,
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OTX_CPT_AES_CBC = 0x3,
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OTX_CPT_AES_ECB = 0x4,
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OTX_CPT_AES_CFB = 0x5,
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OTX_CPT_AES_CTR = 0x6,
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OTX_CPT_AES_GCM = 0x7,
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OTX_CPT_AES_XTS = 0x8
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};
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enum otx_cpt_mac_type {
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OTX_CPT_MAC_NULL = 0x0,
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OTX_CPT_MD5 = 0x1,
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OTX_CPT_SHA1 = 0x2,
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OTX_CPT_SHA224 = 0x3,
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OTX_CPT_SHA256 = 0x4,
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OTX_CPT_SHA384 = 0x5,
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OTX_CPT_SHA512 = 0x6,
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OTX_CPT_GMAC = 0x7
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};
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enum otx_cpt_aes_key_len {
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OTX_CPT_AES_128_BIT = 0x1,
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OTX_CPT_AES_192_BIT = 0x2,
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OTX_CPT_AES_256_BIT = 0x3
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};
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union otx_cpt_encr_ctrl {
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__be64 flags;
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u64 cflags;
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struct {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 enc_cipher:4;
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u64 reserved1:1;
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u64 aes_key:2;
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u64 iv_source:1;
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u64 mac_type:4;
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u64 reserved2:3;
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u64 auth_input_type:1;
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u64 mac_len:8;
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u64 reserved3:8;
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u64 encr_offset:16;
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u64 iv_offset:8;
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u64 auth_offset:8;
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#else
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u64 auth_offset:8;
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u64 iv_offset:8;
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u64 encr_offset:16;
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u64 reserved3:8;
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u64 mac_len:8;
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u64 auth_input_type:1;
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u64 reserved2:3;
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u64 mac_type:4;
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u64 iv_source:1;
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u64 aes_key:2;
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u64 reserved1:1;
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u64 enc_cipher:4;
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#endif
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} e;
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};
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struct otx_cpt_cipher {
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const char *name;
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u8 value;
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};
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struct otx_cpt_enc_context {
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union otx_cpt_encr_ctrl enc_ctrl;
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u8 encr_key[32];
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u8 encr_iv[16];
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};
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union otx_cpt_fchmac_ctx {
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struct {
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u8 ipad[64];
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u8 opad[64];
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} e;
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struct {
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u8 hmac_calc[64]; /* HMAC calculated */
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u8 hmac_recv[64]; /* HMAC received */
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} s;
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};
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struct otx_cpt_fc_ctx {
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struct otx_cpt_enc_context enc;
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union otx_cpt_fchmac_ctx hmac;
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};
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struct otx_cpt_enc_ctx {
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u32 key_len;
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u8 enc_key[OTX_CPT_MAX_KEY_SIZE];
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u8 cipher_type;
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u8 key_type;
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};
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struct otx_cpt_des3_ctx {
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u32 key_len;
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u8 des3_key[OTX_CPT_MAX_KEY_SIZE];
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};
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union otx_cpt_offset_ctrl_word {
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__be64 flags;
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u64 cflags;
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struct {
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#if defined(__BIG_ENDIAN_BITFIELD)
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u64 reserved:32;
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u64 enc_data_offset:16;
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u64 iv_offset:8;
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u64 auth_offset:8;
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#else
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u64 auth_offset:8;
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u64 iv_offset:8;
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u64 enc_data_offset:16;
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u64 reserved:32;
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#endif
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} e;
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};
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struct otx_cpt_req_ctx {
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struct otx_cpt_req_info cpt_req;
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union otx_cpt_offset_ctrl_word ctrl_word;
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struct otx_cpt_fc_ctx fctx;
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};
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struct otx_cpt_sdesc {
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struct shash_desc shash;
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};
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struct otx_cpt_aead_ctx {
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u8 key[OTX_CPT_MAX_KEY_SIZE];
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struct crypto_shash *hashalg;
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struct otx_cpt_sdesc *sdesc;
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u8 *ipad;
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u8 *opad;
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u32 enc_key_len;
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u32 auth_key_len;
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u8 cipher_type;
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u8 mac_type;
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u8 key_type;
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u8 is_trunc_hmac;
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};
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int otx_cpt_crypto_init(struct pci_dev *pdev, struct module *mod,
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enum otx_cptpf_type pf_type,
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enum otx_cptvf_type engine_type,
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int num_queues, int num_devices);
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void otx_cpt_crypto_exit(struct pci_dev *pdev, struct module *mod,
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enum otx_cptvf_type engine_type);
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void otx_cpt_callback(int status, void *arg, void *req);
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#endif /* __OTX_CPT_ALGS_H */
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