/* SPDX-License-Identifier: GPL-2.0-or-later */
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/**
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* AMCC SoC PPC4xx Crypto Driver
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*
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* Copyright (c) 2008 Applied Micro Circuits Corporation.
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* All rights reserved. James Hsiao <jhsiao@amcc.com>
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*
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* This filr defines the register set for Security Subsystem
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*/
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#ifndef __CRYPTO4XX_REG_DEF_H__
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#define __CRYPTO4XX_REG_DEF_H__
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/* CRYPTO4XX Register offset */
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#define CRYPTO4XX_DESCRIPTOR 0x00000000
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#define CRYPTO4XX_CTRL_STAT 0x00000000
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#define CRYPTO4XX_SOURCE 0x00000004
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#define CRYPTO4XX_DEST 0x00000008
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#define CRYPTO4XX_SA 0x0000000C
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#define CRYPTO4XX_SA_LENGTH 0x00000010
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#define CRYPTO4XX_LENGTH 0x00000014
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#define CRYPTO4XX_PE_DMA_CFG 0x00000040
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#define CRYPTO4XX_PE_DMA_STAT 0x00000044
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#define CRYPTO4XX_PDR_BASE 0x00000048
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#define CRYPTO4XX_RDR_BASE 0x0000004c
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#define CRYPTO4XX_RING_SIZE 0x00000050
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#define CRYPTO4XX_RING_CTRL 0x00000054
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#define CRYPTO4XX_INT_RING_STAT 0x00000058
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#define CRYPTO4XX_EXT_RING_STAT 0x0000005c
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#define CRYPTO4XX_IO_THRESHOLD 0x00000060
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#define CRYPTO4XX_GATH_RING_BASE 0x00000064
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#define CRYPTO4XX_SCAT_RING_BASE 0x00000068
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#define CRYPTO4XX_PART_RING_SIZE 0x0000006c
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#define CRYPTO4XX_PART_RING_CFG 0x00000070
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#define CRYPTO4XX_PDR_BASE_UADDR 0x00000080
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#define CRYPTO4XX_RDR_BASE_UADDR 0x00000084
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#define CRYPTO4XX_PKT_SRC_UADDR 0x00000088
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#define CRYPTO4XX_PKT_DEST_UADDR 0x0000008c
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#define CRYPTO4XX_SA_UADDR 0x00000090
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#define CRYPTO4XX_GATH_RING_BASE_UADDR 0x000000A0
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#define CRYPTO4XX_SCAT_RING_BASE_UADDR 0x000000A4
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#define CRYPTO4XX_SEQ_RD 0x00000408
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#define CRYPTO4XX_SEQ_MASK_RD 0x0000040C
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#define CRYPTO4XX_SA_CMD_0 0x00010600
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#define CRYPTO4XX_SA_CMD_1 0x00010604
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#define CRYPTO4XX_STATE_PTR 0x000106dc
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#define CRYPTO4XX_STATE_IV 0x00010700
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#define CRYPTO4XX_STATE_HASH_BYTE_CNT_0 0x00010710
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#define CRYPTO4XX_STATE_HASH_BYTE_CNT_1 0x00010714
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#define CRYPTO4XX_STATE_IDIGEST_0 0x00010718
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#define CRYPTO4XX_STATE_IDIGEST_1 0x0001071c
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#define CRYPTO4XX_DATA_IN 0x00018000
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#define CRYPTO4XX_DATA_OUT 0x0001c000
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#define CRYPTO4XX_INT_UNMASK_STAT 0x000500a0
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#define CRYPTO4XX_INT_MASK_STAT 0x000500a4
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#define CRYPTO4XX_INT_CLR 0x000500a4
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#define CRYPTO4XX_INT_EN 0x000500a8
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#define CRYPTO4XX_INT_PKA 0x00000002
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#define CRYPTO4XX_INT_PDR_DONE 0x00008000
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#define CRYPTO4XX_INT_MA_WR_ERR 0x00020000
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#define CRYPTO4XX_INT_MA_RD_ERR 0x00010000
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#define CRYPTO4XX_INT_PE_ERR 0x00000200
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#define CRYPTO4XX_INT_USER_DMA_ERR 0x00000040
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#define CRYPTO4XX_INT_SLAVE_ERR 0x00000010
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#define CRYPTO4XX_INT_MASTER_ERR 0x00000008
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#define CRYPTO4XX_INT_ERROR 0x00030258
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#define CRYPTO4XX_INT_CFG 0x000500ac
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#define CRYPTO4XX_INT_DESCR_RD 0x000500b0
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#define CRYPTO4XX_INT_DESCR_CNT 0x000500b4
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#define CRYPTO4XX_INT_TIMEOUT_CNT 0x000500b8
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#define CRYPTO4XX_DEVICE_CTRL 0x00060080
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#define CRYPTO4XX_DEVICE_ID 0x00060084
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#define CRYPTO4XX_DEVICE_INFO 0x00060088
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#define CRYPTO4XX_DMA_USER_SRC 0x00060094
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#define CRYPTO4XX_DMA_USER_DEST 0x00060098
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#define CRYPTO4XX_DMA_USER_CMD 0x0006009C
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#define CRYPTO4XX_DMA_CFG 0x000600d4
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#define CRYPTO4XX_BYTE_ORDER_CFG 0x000600d8
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#define CRYPTO4XX_ENDIAN_CFG 0x000600d8
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#define CRYPTO4XX_PRNG_STAT 0x00070000
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#define CRYPTO4XX_PRNG_STAT_BUSY 0x1
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#define CRYPTO4XX_PRNG_CTRL 0x00070004
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#define CRYPTO4XX_PRNG_SEED_L 0x00070008
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#define CRYPTO4XX_PRNG_SEED_H 0x0007000c
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#define CRYPTO4XX_PRNG_RES_0 0x00070020
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#define CRYPTO4XX_PRNG_RES_1 0x00070024
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#define CRYPTO4XX_PRNG_RES_2 0x00070028
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#define CRYPTO4XX_PRNG_RES_3 0x0007002C
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#define CRYPTO4XX_PRNG_LFSR_L 0x00070030
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#define CRYPTO4XX_PRNG_LFSR_H 0x00070034
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/**
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* Initialize CRYPTO ENGINE registers, and memory bases.
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*/
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#define PPC4XX_PDR_POLL 0x3ff
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#define PPC4XX_OUTPUT_THRESHOLD 2
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#define PPC4XX_INPUT_THRESHOLD 2
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#define PPC4XX_PD_SIZE 6
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#define PPC4XX_CTX_DONE_INT 0x2000
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#define PPC4XX_PD_DONE_INT 0x8000
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#define PPC4XX_TMO_ERR_INT 0x40000
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#define PPC4XX_BYTE_ORDER 0x22222
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#define PPC4XX_INTERRUPT_CLR 0x3ffff
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#define PPC4XX_PRNG_CTRL_AUTO_EN 0x3
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#define PPC4XX_DC_3DES_EN 1
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#define PPC4XX_TRNG_EN 0x00020000
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#define PPC4XX_INT_DESCR_CNT 7
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#define PPC4XX_INT_TIMEOUT_CNT 0
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#define PPC4XX_INT_TIMEOUT_CNT_REVB 0x3FF
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#define PPC4XX_INT_CFG 1
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/**
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* all follow define are ad hoc
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*/
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#define PPC4XX_RING_RETRY 100
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#define PPC4XX_RING_POLL 100
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#define PPC4XX_SDR_SIZE PPC4XX_NUM_SD
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#define PPC4XX_GDR_SIZE PPC4XX_NUM_GD
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/**
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* Generic Security Association (SA) with all possible fields. These will
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* never likely used except for reference purpose. These structure format
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* can be not changed as the hardware expects them to be layout as defined.
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* Field can be removed or reduced but ordering can not be changed.
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*/
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#define CRYPTO4XX_DMA_CFG_OFFSET 0x40
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union ce_pe_dma_cfg {
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struct {
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u32 rsv:7;
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u32 dir_host:1;
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u32 rsv1:2;
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u32 bo_td_en:1;
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u32 dis_pdr_upd:1;
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u32 bo_sgpd_en:1;
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u32 bo_data_en:1;
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u32 bo_sa_en:1;
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u32 bo_pd_en:1;
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u32 rsv2:4;
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u32 dynamic_sa_en:1;
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u32 pdr_mode:2;
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u32 pe_mode:1;
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u32 rsv3:5;
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u32 reset_sg:1;
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u32 reset_pdr:1;
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u32 reset_pe:1;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define CRYPTO4XX_PDR_BASE_OFFSET 0x48
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#define CRYPTO4XX_RDR_BASE_OFFSET 0x4c
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#define CRYPTO4XX_RING_SIZE_OFFSET 0x50
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union ce_ring_size {
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struct {
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u32 ring_offset:16;
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u32 rsv:6;
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u32 ring_size:10;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define CRYPTO4XX_RING_CONTROL_OFFSET 0x54
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union ce_ring_control {
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struct {
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u32 continuous:1;
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u32 rsv:5;
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u32 ring_retry_divisor:10;
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u32 rsv1:4;
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u32 ring_poll_divisor:10;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define CRYPTO4XX_IO_THRESHOLD_OFFSET 0x60
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union ce_io_threshold {
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struct {
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u32 rsv:6;
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u32 output_threshold:10;
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u32 rsv1:6;
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u32 input_threshold:10;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define CRYPTO4XX_GATHER_RING_BASE_OFFSET 0x64
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#define CRYPTO4XX_SCATTER_RING_BASE_OFFSET 0x68
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union ce_part_ring_size {
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struct {
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u32 sdr_size:16;
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u32 gdr_size:16;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define MAX_BURST_SIZE_32 0
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#define MAX_BURST_SIZE_64 1
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#define MAX_BURST_SIZE_128 2
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#define MAX_BURST_SIZE_256 3
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/* gather descriptor control length */
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struct gd_ctl_len {
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u32 len:16;
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u32 rsv:14;
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u32 done:1;
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u32 ready:1;
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} __attribute__((packed));
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struct ce_gd {
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u32 ptr;
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struct gd_ctl_len ctl_len;
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} __attribute__((packed));
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struct sd_ctl {
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u32 ctl:30;
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u32 done:1;
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u32 rdy:1;
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} __attribute__((packed));
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struct ce_sd {
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u32 ptr;
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struct sd_ctl ctl;
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} __attribute__((packed));
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#define PD_PAD_CTL_32 0x10
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#define PD_PAD_CTL_64 0x20
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#define PD_PAD_CTL_128 0x40
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#define PD_PAD_CTL_256 0x80
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union ce_pd_ctl {
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struct {
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u32 pd_pad_ctl:8;
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u32 status:8;
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u32 next_hdr:8;
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u32 rsv:2;
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u32 cached_sa:1;
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u32 hash_final:1;
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u32 init_arc4:1;
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u32 rsv1:1;
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u32 pe_done:1;
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u32 host_ready:1;
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} bf;
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u32 w;
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} __attribute__((packed));
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#define PD_CTL_HASH_FINAL BIT(4)
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#define PD_CTL_PE_DONE BIT(1)
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#define PD_CTL_HOST_READY BIT(0)
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union ce_pd_ctl_len {
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struct {
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u32 bypass:8;
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u32 pe_done:1;
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u32 host_ready:1;
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u32 rsv:2;
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u32 pkt_len:20;
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} bf;
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u32 w;
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} __attribute__((packed));
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struct ce_pd {
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union ce_pd_ctl pd_ctl;
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u32 src;
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u32 dest;
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u32 sa; /* get from ctx->sa_dma_addr */
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u32 sa_len; /* only if dynamic sa is used */
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union ce_pd_ctl_len pd_ctl_len;
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} __attribute__((packed));
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#endif
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