/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_TLB_H
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#define _ASM_X86_TLB_H
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
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#define tlb_flush tlb_flush
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static inline void tlb_flush(struct mmu_gather *tlb);
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#include <asm-generic/tlb.h>
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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unsigned long start = 0UL, end = TLB_FLUSH_ALL;
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unsigned int stride_shift = tlb_get_unmap_shift(tlb);
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if (!tlb->fullmm && !tlb->need_flush_all) {
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start = tlb->start;
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end = tlb->end;
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}
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flush_tlb_mm_range(tlb->mm, start, end, stride_shift, tlb->freed_tables);
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}
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/*
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* While x86 architecture in general requires an IPI to perform TLB
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* shootdown, enablement code for several hypervisors overrides
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* .flush_tlb_others hook in pv_mmu_ops and implements it by issuing
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* a hypercall. To keep software pagetable walkers safe in this case we
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* switch to RCU based table free (MMU_GATHER_RCU_TABLE_FREE). See the comment
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* below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
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* for more details.
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*/
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static inline void __tlb_remove_table(void *table)
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{
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free_page_and_swap_cache(table);
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}
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#endif /* _ASM_X86_TLB_H */
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