/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_SPECIAL_INSNS_H
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#define _ASM_X86_SPECIAL_INSNS_H
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#ifdef __KERNEL__
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#include <asm/nops.h>
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#include <asm/processor-flags.h>
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#include <linux/irqflags.h>
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#include <linux/jump_label.h>
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/*
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* The compiler should not reorder volatile asm statements with respect to each
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* other: they should execute in program order. However GCC 4.9.x and 5.x have
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* a bug (which was fixed in 8.1, 7.3 and 6.5) where they might reorder
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* volatile asm. The write functions are not affected since they have memory
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* clobbers preventing reordering. To prevent reads from being reordered with
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* respect to writes, use a dummy memory operand.
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*/
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#define __FORCE_ORDER "m"(*(unsigned int *)0x1000UL)
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void native_write_cr0(unsigned long val);
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("mov %%cr0,%0\n\t" : "=r" (val) : __FORCE_ORDER);
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return val;
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}
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static __always_inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : __FORCE_ORDER);
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return val;
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}
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static __always_inline void native_write_cr2(unsigned long val)
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{
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asm volatile("mov %0,%%cr2": : "r" (val) : "memory");
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}
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static inline unsigned long __native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER);
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("mov %0,%%cr3": : "r" (val) : "memory");
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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#ifdef CONFIG_X86_32
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/*
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* This could fault if CR4 does not exist. Non-existent CR4
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* is functionally equivalent to CR4 == 0. Keep it simple and pretend
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* that CR4 == 0 on CPUs that don't have CR4.
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*/
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asm volatile("1: mov %%cr4, %0\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b)
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: "=r" (val) : "0" (0), __FORCE_ORDER);
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#else
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/* CR4 always exists on x86_64. */
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asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : __FORCE_ORDER);
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#endif
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return val;
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}
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void native_write_cr4(unsigned long val);
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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static inline u32 rdpkru(void)
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{
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u32 ecx = 0;
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u32 edx, pkru;
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/*
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* "rdpkru" instruction. Places PKRU contents in to EAX,
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* clears EDX and requires that ecx=0.
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*/
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asm volatile(".byte 0x0f,0x01,0xee\n\t"
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: "=a" (pkru), "=d" (edx)
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: "c" (ecx));
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return pkru;
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}
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static inline void wrpkru(u32 pkru)
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{
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u32 ecx = 0, edx = 0;
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/*
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* "wrpkru" instruction. Loads contents in EAX to PKRU,
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* requires that ecx = edx = 0.
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*/
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asm volatile(".byte 0x0f,0x01,0xef\n\t"
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: : "a" (pkru), "c"(ecx), "d"(edx));
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}
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static inline void __write_pkru(u32 pkru)
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{
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/*
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* WRPKRU is relatively expensive compared to RDPKRU.
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* Avoid WRPKRU when it would not change the value.
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*/
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if (pkru == rdpkru())
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return;
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wrpkru(pkru);
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}
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#else
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static inline u32 rdpkru(void)
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{
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return 0;
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}
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static inline void __write_pkru(u32 pkru)
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{
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}
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#endif
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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extern asmlinkage void asm_load_gs_index(unsigned int selector);
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static inline void native_load_gs_index(unsigned int selector)
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{
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unsigned long flags;
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local_irq_save(flags);
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asm_load_gs_index(selector);
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local_irq_restore(flags);
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}
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static inline unsigned long __read_cr4(void)
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{
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return native_read_cr4();
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}
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#ifdef CONFIG_PARAVIRT_XXL
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#include <asm/paravirt.h>
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#else
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static inline unsigned long read_cr0(void)
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{
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return native_read_cr0();
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}
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static inline void write_cr0(unsigned long x)
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{
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native_write_cr0(x);
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}
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static __always_inline unsigned long read_cr2(void)
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{
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return native_read_cr2();
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}
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static __always_inline void write_cr2(unsigned long x)
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{
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native_write_cr2(x);
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}
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/*
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* Careful! CR3 contains more than just an address. You probably want
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* read_cr3_pa() instead.
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*/
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static inline unsigned long __read_cr3(void)
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{
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return __native_read_cr3();
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}
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static inline void write_cr3(unsigned long x)
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{
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native_write_cr3(x);
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}
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static inline void __write_cr4(unsigned long x)
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{
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native_write_cr4(x);
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}
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static inline void wbinvd(void)
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{
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native_wbinvd();
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}
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#ifdef CONFIG_X86_64
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static inline void load_gs_index(unsigned int selector)
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{
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native_load_gs_index(selector);
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}
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#endif
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#endif /* CONFIG_PARAVIRT_XXL */
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static inline void clflush(volatile void *__p)
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{
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asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
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}
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static inline void clflushopt(volatile void *__p)
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{
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alternative_io(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0",
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".byte 0x66; clflush %P0",
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X86_FEATURE_CLFLUSHOPT,
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"+m" (*(volatile char __force *)__p));
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}
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static inline void clwb(volatile void *__p)
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{
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volatile struct { char x[64]; } *p = __p;
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asm volatile(ALTERNATIVE_2(
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".byte " __stringify(NOP_DS_PREFIX) "; clflush (%[pax])",
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".byte 0x66; clflush (%[pax])", /* clflushopt (%%rax) */
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X86_FEATURE_CLFLUSHOPT,
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".byte 0x66, 0x0f, 0xae, 0x30", /* clwb (%%rax) */
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X86_FEATURE_CLWB)
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: [p] "+m" (*p)
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: [pax] "a" (p));
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}
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#define nop() asm volatile ("nop")
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static inline void serialize(void)
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{
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/* Instruction opcode for SERIALIZE; supported in binutils >= 2.35. */
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asm volatile(".byte 0xf, 0x1, 0xe8" ::: "memory");
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}
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/* The dst parameter must be 64-bytes aligned */
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static inline void movdir64b(void *dst, const void *src)
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{
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const struct { char _[64]; } *__src = src;
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struct { char _[64]; } *__dst = dst;
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/*
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* MOVDIR64B %(rdx), rax.
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*
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* Both __src and __dst must be memory constraints in order to tell the
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* compiler that no other memory accesses should be reordered around
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* this one.
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*
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* Also, both must be supplied as lvalues because this tells
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* the compiler what the object is (its size) the instruction accesses.
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* I.e., not the pointers but what they point to, thus the deref'ing '*'.
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*/
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asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02"
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: "+m" (*__dst)
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: "m" (*__src), "a" (__dst), "d" (__src));
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}
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/**
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* enqcmds - Enqueue a command in supervisor (CPL0) mode
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* @dst: destination, in MMIO space (must be 512-bit aligned)
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* @src: 512 bits memory operand
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*
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* The ENQCMDS instruction allows software to write a 512-bit command to
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* a 512-bit-aligned special MMIO region that supports the instruction.
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* A return status is loaded into the ZF flag in the RFLAGS register.
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* ZF = 0 equates to success, and ZF = 1 indicates retry or error.
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*
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* This function issues the ENQCMDS instruction to submit data from
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* kernel space to MMIO space, in a unit of 512 bits. Order of data access
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* is not guaranteed, nor is a memory barrier performed afterwards. It
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* returns 0 on success and -EAGAIN on failure.
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*
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* Warning: Do not use this helper unless your driver has checked that the
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* ENQCMDS instruction is supported on the platform and the device accepts
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* ENQCMDS.
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*/
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static inline int enqcmds(void __iomem *dst, const void *src)
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{
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const struct { char _[64]; } *__src = src;
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struct { char _[64]; } __iomem *__dst = dst;
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bool zf;
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/*
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* ENQCMDS %(rdx), rax
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*
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* See movdir64b()'s comment on operand specification.
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*/
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asm volatile(".byte 0xf3, 0x0f, 0x38, 0xf8, 0x02, 0x66, 0x90"
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CC_SET(z)
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: CC_OUT(z) (zf), "+m" (*__dst)
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: "m" (*__src), "a" (__dst), "d" (__src));
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/* Submission failure is indicated via EFLAGS.ZF=1 */
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if (zf)
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return -EAGAIN;
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return 0;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_SPECIAL_INSNS_H */
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