/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_QSPINLOCK_PARAVIRT_H
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#define __ASM_QSPINLOCK_PARAVIRT_H
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/*
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* For x86-64, PV_CALLEE_SAVE_REGS_THUNK() saves and restores 8 64-bit
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* registers. For i386, however, only 1 32-bit register needs to be saved
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* and restored. So an optimized version of __pv_queued_spin_unlock() is
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* hand-coded for 64-bit, but it isn't worthwhile to do it for 32-bit.
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*/
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#ifdef CONFIG_64BIT
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PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath);
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#define __pv_queued_spin_unlock __pv_queued_spin_unlock
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#define PV_UNLOCK "__raw_callee_save___pv_queued_spin_unlock"
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#define PV_UNLOCK_SLOWPATH "__raw_callee_save___pv_queued_spin_unlock_slowpath"
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/*
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* Optimized assembly version of __raw_callee_save___pv_queued_spin_unlock
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* which combines the registers saving trunk and the body of the following
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* C code:
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*
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* void __pv_queued_spin_unlock(struct qspinlock *lock)
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* {
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* u8 lockval = cmpxchg(&lock->locked, _Q_LOCKED_VAL, 0);
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*
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* if (likely(lockval == _Q_LOCKED_VAL))
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* return;
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* pv_queued_spin_unlock_slowpath(lock, lockval);
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* }
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*
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* For x86-64,
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* rdi = lock (first argument)
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* rsi = lockval (second argument)
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* rdx = internal variable (set to 0)
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*/
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asm (".pushsection .text;"
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".globl " PV_UNLOCK ";"
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".type " PV_UNLOCK ", @function;"
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".align 4,0x90;"
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PV_UNLOCK ": "
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FRAME_BEGIN
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"push %rdx;"
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"mov $0x1,%eax;"
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"xor %edx,%edx;"
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LOCK_PREFIX "cmpxchg %dl,(%rdi);"
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"cmp $0x1,%al;"
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"jne .slowpath;"
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"pop %rdx;"
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FRAME_END
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ASM_RET
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".slowpath: "
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"push %rsi;"
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"movzbl %al,%esi;"
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"call " PV_UNLOCK_SLOWPATH ";"
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"pop %rsi;"
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"pop %rdx;"
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FRAME_END
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ASM_RET
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".size " PV_UNLOCK ", .-" PV_UNLOCK ";"
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".popsection");
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#else /* CONFIG_64BIT */
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extern void __pv_queued_spin_unlock(struct qspinlock *lock);
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PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock);
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#endif /* CONFIG_64BIT */
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#endif
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