/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PERCPU_H
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#define _ASM_X86_PERCPU_H
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#ifdef CONFIG_X86_64
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#define __percpu_seg gs
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#else
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#define __percpu_seg fs
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#endif
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#ifdef __ASSEMBLY__
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#ifdef CONFIG_SMP
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#define PER_CPU_VAR(var) %__percpu_seg:var
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#else /* ! SMP */
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#define PER_CPU_VAR(var) var
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#endif /* SMP */
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#ifdef CONFIG_X86_64_SMP
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#define INIT_PER_CPU_VAR(var) init_per_cpu__##var
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#else
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#define INIT_PER_CPU_VAR(var) var
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#endif
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#else /* ...!ASSEMBLY */
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#include <linux/kernel.h>
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#include <linux/stringify.h>
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#ifdef CONFIG_SMP
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#define __percpu_prefix "%%"__stringify(__percpu_seg)":"
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#define __my_cpu_offset this_cpu_read(this_cpu_off)
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/*
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* Compared to the generic __my_cpu_offset version, the following
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* saves one instruction and avoids clobbering a temp register.
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*/
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#define arch_raw_cpu_ptr(ptr) \
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({ \
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unsigned long tcp_ptr__; \
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asm volatile("add " __percpu_arg(1) ", %0" \
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: "=r" (tcp_ptr__) \
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: "m" (this_cpu_off), "0" (ptr)); \
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(typeof(*(ptr)) __kernel __force *)tcp_ptr__; \
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})
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#else
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#define __percpu_prefix ""
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#endif
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#define __percpu_arg(x) __percpu_prefix "%" #x
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/*
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* Initialized pointers to per-cpu variables needed for the boot
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* processor need to use these macros to get the proper address
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* offset from __per_cpu_load on SMP.
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*
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* There also must be an entry in vmlinux_64.lds.S
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*/
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#define DECLARE_INIT_PER_CPU(var) \
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extern typeof(var) init_per_cpu_var(var)
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#ifdef CONFIG_X86_64_SMP
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#define init_per_cpu_var(var) init_per_cpu__##var
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#else
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#define init_per_cpu_var(var) var
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#endif
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/* For arch-specific code, we can use direct single-insn ops (they
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* don't give an lvalue though). */
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#define __pcpu_type_1 u8
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#define __pcpu_type_2 u16
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#define __pcpu_type_4 u32
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#define __pcpu_type_8 u64
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#define __pcpu_cast_1(val) ((u8)(((unsigned long) val) & 0xff))
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#define __pcpu_cast_2(val) ((u16)(((unsigned long) val) & 0xffff))
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#define __pcpu_cast_4(val) ((u32)(((unsigned long) val) & 0xffffffff))
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#define __pcpu_cast_8(val) ((u64)(val))
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#define __pcpu_op1_1(op, dst) op "b " dst
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#define __pcpu_op1_2(op, dst) op "w " dst
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#define __pcpu_op1_4(op, dst) op "l " dst
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#define __pcpu_op1_8(op, dst) op "q " dst
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#define __pcpu_op2_1(op, src, dst) op "b " src ", " dst
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#define __pcpu_op2_2(op, src, dst) op "w " src ", " dst
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#define __pcpu_op2_4(op, src, dst) op "l " src ", " dst
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#define __pcpu_op2_8(op, src, dst) op "q " src ", " dst
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#define __pcpu_reg_1(mod, x) mod "q" (x)
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#define __pcpu_reg_2(mod, x) mod "r" (x)
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#define __pcpu_reg_4(mod, x) mod "r" (x)
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#define __pcpu_reg_8(mod, x) mod "r" (x)
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#define __pcpu_reg_imm_1(x) "qi" (x)
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#define __pcpu_reg_imm_2(x) "ri" (x)
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#define __pcpu_reg_imm_4(x) "ri" (x)
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#define __pcpu_reg_imm_8(x) "re" (x)
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#define percpu_to_op(size, qual, op, _var, _val) \
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do { \
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__pcpu_type_##size pto_val__ = __pcpu_cast_##size(_val); \
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if (0) { \
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typeof(_var) pto_tmp__; \
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pto_tmp__ = (_val); \
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(void)pto_tmp__; \
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} \
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asm qual(__pcpu_op2_##size(op, "%[val]", __percpu_arg([var])) \
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: [var] "+m" (_var) \
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: [val] __pcpu_reg_imm_##size(pto_val__)); \
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} while (0)
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#define percpu_unary_op(size, qual, op, _var) \
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({ \
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asm qual (__pcpu_op1_##size(op, __percpu_arg([var])) \
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: [var] "+m" (_var)); \
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})
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/*
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* Generate a percpu add to memory instruction and optimize code
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* if one is added or subtracted.
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*/
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#define percpu_add_op(size, qual, var, val) \
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do { \
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const int pao_ID__ = (__builtin_constant_p(val) && \
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((val) == 1 || (val) == -1)) ? \
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(int)(val) : 0; \
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if (0) { \
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typeof(var) pao_tmp__; \
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pao_tmp__ = (val); \
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(void)pao_tmp__; \
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} \
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if (pao_ID__ == 1) \
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percpu_unary_op(size, qual, "inc", var); \
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else if (pao_ID__ == -1) \
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percpu_unary_op(size, qual, "dec", var); \
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else \
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percpu_to_op(size, qual, "add", var, val); \
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} while (0)
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#define percpu_from_op(size, qual, op, _var) \
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({ \
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__pcpu_type_##size pfo_val__; \
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asm qual (__pcpu_op2_##size(op, __percpu_arg([var]), "%[val]") \
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: [val] __pcpu_reg_##size("=", pfo_val__) \
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: [var] "m" (_var)); \
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(typeof(_var))(unsigned long) pfo_val__; \
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})
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#define percpu_stable_op(size, op, _var) \
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({ \
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__pcpu_type_##size pfo_val__; \
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asm(__pcpu_op2_##size(op, __percpu_arg(P[var]), "%[val]") \
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: [val] __pcpu_reg_##size("=", pfo_val__) \
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: [var] "p" (&(_var))); \
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(typeof(_var))(unsigned long) pfo_val__; \
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})
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/*
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* Add return operation
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*/
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#define percpu_add_return_op(size, qual, _var, _val) \
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({ \
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__pcpu_type_##size paro_tmp__ = __pcpu_cast_##size(_val); \
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asm qual (__pcpu_op2_##size("xadd", "%[tmp]", \
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__percpu_arg([var])) \
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: [tmp] __pcpu_reg_##size("+", paro_tmp__), \
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[var] "+m" (_var) \
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: : "memory"); \
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(typeof(_var))(unsigned long) (paro_tmp__ + _val); \
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})
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/*
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* xchg is implemented using cmpxchg without a lock prefix. xchg is
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* expensive due to the implied lock prefix. The processor cannot prefetch
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* cachelines if xchg is used.
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*/
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#define percpu_xchg_op(size, qual, _var, _nval) \
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({ \
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__pcpu_type_##size pxo_old__; \
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__pcpu_type_##size pxo_new__ = __pcpu_cast_##size(_nval); \
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asm qual (__pcpu_op2_##size("mov", __percpu_arg([var]), \
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"%[oval]") \
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"\n1:\t" \
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__pcpu_op2_##size("cmpxchg", "%[nval]", \
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__percpu_arg([var])) \
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"\n\tjnz 1b" \
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: [oval] "=&a" (pxo_old__), \
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[var] "+m" (_var) \
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: [nval] __pcpu_reg_##size(, pxo_new__) \
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: "memory"); \
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(typeof(_var))(unsigned long) pxo_old__; \
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})
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/*
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* cmpxchg has no such implied lock semantics as a result it is much
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* more efficient for cpu local operations.
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*/
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#define percpu_cmpxchg_op(size, qual, _var, _oval, _nval) \
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({ \
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__pcpu_type_##size pco_old__ = __pcpu_cast_##size(_oval); \
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__pcpu_type_##size pco_new__ = __pcpu_cast_##size(_nval); \
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asm qual (__pcpu_op2_##size("cmpxchg", "%[nval]", \
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__percpu_arg([var])) \
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: [oval] "+a" (pco_old__), \
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[var] "+m" (_var) \
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: [nval] __pcpu_reg_##size(, pco_new__) \
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: "memory"); \
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(typeof(_var))(unsigned long) pco_old__; \
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})
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/*
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* this_cpu_read() makes gcc load the percpu variable every time it is
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* accessed while this_cpu_read_stable() allows the value to be cached.
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* this_cpu_read_stable() is more efficient and can be used if its value
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* is guaranteed to be valid across cpus. The current users include
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* get_current() and get_thread_info() both of which are actually
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* per-thread variables implemented as per-cpu variables and thus
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* stable for the duration of the respective task.
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*/
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#define this_cpu_read_stable_1(pcp) percpu_stable_op(1, "mov", pcp)
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#define this_cpu_read_stable_2(pcp) percpu_stable_op(2, "mov", pcp)
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#define this_cpu_read_stable_4(pcp) percpu_stable_op(4, "mov", pcp)
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#define this_cpu_read_stable_8(pcp) percpu_stable_op(8, "mov", pcp)
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#define this_cpu_read_stable(pcp) __pcpu_size_call_return(this_cpu_read_stable_, pcp)
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#define raw_cpu_read_1(pcp) percpu_from_op(1, , "mov", pcp)
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#define raw_cpu_read_2(pcp) percpu_from_op(2, , "mov", pcp)
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#define raw_cpu_read_4(pcp) percpu_from_op(4, , "mov", pcp)
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#define raw_cpu_write_1(pcp, val) percpu_to_op(1, , "mov", (pcp), val)
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#define raw_cpu_write_2(pcp, val) percpu_to_op(2, , "mov", (pcp), val)
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#define raw_cpu_write_4(pcp, val) percpu_to_op(4, , "mov", (pcp), val)
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#define raw_cpu_add_1(pcp, val) percpu_add_op(1, , (pcp), val)
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#define raw_cpu_add_2(pcp, val) percpu_add_op(2, , (pcp), val)
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#define raw_cpu_add_4(pcp, val) percpu_add_op(4, , (pcp), val)
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#define raw_cpu_and_1(pcp, val) percpu_to_op(1, , "and", (pcp), val)
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#define raw_cpu_and_2(pcp, val) percpu_to_op(2, , "and", (pcp), val)
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#define raw_cpu_and_4(pcp, val) percpu_to_op(4, , "and", (pcp), val)
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#define raw_cpu_or_1(pcp, val) percpu_to_op(1, , "or", (pcp), val)
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#define raw_cpu_or_2(pcp, val) percpu_to_op(2, , "or", (pcp), val)
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#define raw_cpu_or_4(pcp, val) percpu_to_op(4, , "or", (pcp), val)
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/*
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* raw_cpu_xchg() can use a load-store since it is not required to be
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* IRQ-safe.
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*/
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#define raw_percpu_xchg_op(var, nval) \
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({ \
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typeof(var) pxo_ret__ = raw_cpu_read(var); \
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raw_cpu_write(var, (nval)); \
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pxo_ret__; \
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})
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#define raw_cpu_xchg_1(pcp, val) raw_percpu_xchg_op(pcp, val)
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#define raw_cpu_xchg_2(pcp, val) raw_percpu_xchg_op(pcp, val)
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#define raw_cpu_xchg_4(pcp, val) raw_percpu_xchg_op(pcp, val)
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#define this_cpu_read_1(pcp) percpu_from_op(1, volatile, "mov", pcp)
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#define this_cpu_read_2(pcp) percpu_from_op(2, volatile, "mov", pcp)
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#define this_cpu_read_4(pcp) percpu_from_op(4, volatile, "mov", pcp)
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#define this_cpu_write_1(pcp, val) percpu_to_op(1, volatile, "mov", (pcp), val)
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#define this_cpu_write_2(pcp, val) percpu_to_op(2, volatile, "mov", (pcp), val)
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#define this_cpu_write_4(pcp, val) percpu_to_op(4, volatile, "mov", (pcp), val)
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#define this_cpu_add_1(pcp, val) percpu_add_op(1, volatile, (pcp), val)
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#define this_cpu_add_2(pcp, val) percpu_add_op(2, volatile, (pcp), val)
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#define this_cpu_add_4(pcp, val) percpu_add_op(4, volatile, (pcp), val)
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#define this_cpu_and_1(pcp, val) percpu_to_op(1, volatile, "and", (pcp), val)
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#define this_cpu_and_2(pcp, val) percpu_to_op(2, volatile, "and", (pcp), val)
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#define this_cpu_and_4(pcp, val) percpu_to_op(4, volatile, "and", (pcp), val)
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#define this_cpu_or_1(pcp, val) percpu_to_op(1, volatile, "or", (pcp), val)
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#define this_cpu_or_2(pcp, val) percpu_to_op(2, volatile, "or", (pcp), val)
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#define this_cpu_or_4(pcp, val) percpu_to_op(4, volatile, "or", (pcp), val)
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#define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(1, volatile, pcp, nval)
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#define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(2, volatile, pcp, nval)
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#define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(4, volatile, pcp, nval)
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#define raw_cpu_add_return_1(pcp, val) percpu_add_return_op(1, , pcp, val)
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#define raw_cpu_add_return_2(pcp, val) percpu_add_return_op(2, , pcp, val)
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#define raw_cpu_add_return_4(pcp, val) percpu_add_return_op(4, , pcp, val)
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#define raw_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(1, , pcp, oval, nval)
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#define raw_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(2, , pcp, oval, nval)
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#define raw_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(4, , pcp, oval, nval)
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#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(1, volatile, pcp, val)
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#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(2, volatile, pcp, val)
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#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(4, volatile, pcp, val)
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#define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(1, volatile, pcp, oval, nval)
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#define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(2, volatile, pcp, oval, nval)
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#define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(4, volatile, pcp, oval, nval)
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#ifdef CONFIG_X86_CMPXCHG64
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#define percpu_cmpxchg8b_double(pcp1, pcp2, o1, o2, n1, n2) \
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({ \
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bool __ret; \
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typeof(pcp1) __o1 = (o1), __n1 = (n1); \
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typeof(pcp2) __o2 = (o2), __n2 = (n2); \
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asm volatile("cmpxchg8b "__percpu_arg(1) \
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CC_SET(z) \
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: CC_OUT(z) (__ret), "+m" (pcp1), "+m" (pcp2), "+a" (__o1), "+d" (__o2) \
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: "b" (__n1), "c" (__n2)); \
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__ret; \
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})
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#define raw_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double
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#define this_cpu_cmpxchg_double_4 percpu_cmpxchg8b_double
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#endif /* CONFIG_X86_CMPXCHG64 */
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/*
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* Per cpu atomic 64 bit operations are only available under 64 bit.
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* 32 bit must fall back to generic operations.
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*/
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#ifdef CONFIG_X86_64
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#define raw_cpu_read_8(pcp) percpu_from_op(8, , "mov", pcp)
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#define raw_cpu_write_8(pcp, val) percpu_to_op(8, , "mov", (pcp), val)
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#define raw_cpu_add_8(pcp, val) percpu_add_op(8, , (pcp), val)
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#define raw_cpu_and_8(pcp, val) percpu_to_op(8, , "and", (pcp), val)
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#define raw_cpu_or_8(pcp, val) percpu_to_op(8, , "or", (pcp), val)
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#define raw_cpu_add_return_8(pcp, val) percpu_add_return_op(8, , pcp, val)
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#define raw_cpu_xchg_8(pcp, nval) raw_percpu_xchg_op(pcp, nval)
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#define raw_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(8, , pcp, oval, nval)
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#define this_cpu_read_8(pcp) percpu_from_op(8, volatile, "mov", pcp)
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#define this_cpu_write_8(pcp, val) percpu_to_op(8, volatile, "mov", (pcp), val)
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#define this_cpu_add_8(pcp, val) percpu_add_op(8, volatile, (pcp), val)
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#define this_cpu_and_8(pcp, val) percpu_to_op(8, volatile, "and", (pcp), val)
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#define this_cpu_or_8(pcp, val) percpu_to_op(8, volatile, "or", (pcp), val)
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#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(8, volatile, pcp, val)
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#define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(8, volatile, pcp, nval)
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#define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(8, volatile, pcp, oval, nval)
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/*
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* Pretty complex macro to generate cmpxchg16 instruction. The instruction
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* is not supported on early AMD64 processors so we must be able to emulate
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* it in software. The address used in the cmpxchg16 instruction must be
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* aligned to a 16 byte boundary.
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*/
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#define percpu_cmpxchg16b_double(pcp1, pcp2, o1, o2, n1, n2) \
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({ \
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bool __ret; \
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typeof(pcp1) __o1 = (o1), __n1 = (n1); \
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typeof(pcp2) __o2 = (o2), __n2 = (n2); \
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alternative_io("leaq %P1,%%rsi\n\tcall this_cpu_cmpxchg16b_emu\n\t", \
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"cmpxchg16b " __percpu_arg(1) "\n\tsetz %0\n\t", \
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X86_FEATURE_CX16, \
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ASM_OUTPUT2("=a" (__ret), "+m" (pcp1), \
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"+m" (pcp2), "+d" (__o2)), \
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"b" (__n1), "c" (__n2), "a" (__o1) : "rsi"); \
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__ret; \
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})
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#define raw_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double
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#define this_cpu_cmpxchg_double_8 percpu_cmpxchg16b_double
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#endif
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static __always_inline bool x86_this_cpu_constant_test_bit(unsigned int nr,
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const unsigned long __percpu *addr)
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{
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unsigned long __percpu *a =
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(unsigned long __percpu *)addr + nr / BITS_PER_LONG;
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#ifdef CONFIG_X86_64
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return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_8(*a)) != 0;
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#else
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return ((1UL << (nr % BITS_PER_LONG)) & raw_cpu_read_4(*a)) != 0;
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#endif
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}
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static inline bool x86_this_cpu_variable_test_bit(int nr,
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const unsigned long __percpu *addr)
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{
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bool oldbit;
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asm volatile("btl "__percpu_arg(2)",%1"
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CC_SET(c)
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: CC_OUT(c) (oldbit)
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: "m" (*(unsigned long __percpu *)addr), "Ir" (nr));
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return oldbit;
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}
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#define x86_this_cpu_test_bit(nr, addr) \
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(__builtin_constant_p((nr)) \
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? x86_this_cpu_constant_test_bit((nr), (addr)) \
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: x86_this_cpu_variable_test_bit((nr), (addr)))
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#include <asm-generic/percpu.h>
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/* We can use this directly for local CPU (faster). */
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DECLARE_PER_CPU_READ_MOSTLY(unsigned long, this_cpu_off);
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#endif /* !__ASSEMBLY__ */
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#ifdef CONFIG_SMP
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/*
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* Define the "EARLY_PER_CPU" macros. These are used for some per_cpu
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* variables that are initialized and accessed before there are per_cpu
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* areas allocated.
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*/
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#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
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DEFINE_PER_CPU(_type, _name) = _initvalue; \
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__typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
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{ [0 ... NR_CPUS-1] = _initvalue }; \
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__typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
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#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \
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DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue; \
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__typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
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{ [0 ... NR_CPUS-1] = _initvalue }; \
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__typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
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#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
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EXPORT_PER_CPU_SYMBOL(_name)
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#define DECLARE_EARLY_PER_CPU(_type, _name) \
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DECLARE_PER_CPU(_type, _name); \
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extern __typeof__(_type) *_name##_early_ptr; \
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extern __typeof__(_type) _name##_early_map[]
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#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \
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DECLARE_PER_CPU_READ_MOSTLY(_type, _name); \
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extern __typeof__(_type) *_name##_early_ptr; \
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extern __typeof__(_type) _name##_early_map[]
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#define early_per_cpu_ptr(_name) (_name##_early_ptr)
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#define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
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#define early_per_cpu(_name, _cpu) \
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*(early_per_cpu_ptr(_name) ? \
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&early_per_cpu_ptr(_name)[_cpu] : \
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&per_cpu(_name, _cpu))
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#else /* !CONFIG_SMP */
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#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
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DEFINE_PER_CPU(_type, _name) = _initvalue
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#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue) \
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DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue
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#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
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EXPORT_PER_CPU_SYMBOL(_name)
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#define DECLARE_EARLY_PER_CPU(_type, _name) \
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DECLARE_PER_CPU(_type, _name)
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#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name) \
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DECLARE_PER_CPU_READ_MOSTLY(_type, _name)
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#define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
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#define early_per_cpu_ptr(_name) NULL
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/* no early_per_cpu_map() */
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#endif /* !CONFIG_SMP */
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#endif /* _ASM_X86_PERCPU_H */
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