/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MPSPEC_H
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#define _ASM_X86_MPSPEC_H
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#include <asm/mpspec_def.h>
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#include <asm/x86_init.h>
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#include <asm/apicdef.h>
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extern int pic_mode;
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#ifdef CONFIG_X86_32
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/*
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* Summit or generic (i.e. installer) kernels need lots of bus entries.
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* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
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*/
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#if CONFIG_BASE_SMALL == 0
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# define MAX_MP_BUSSES 260
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#else
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# define MAX_MP_BUSSES 32
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#endif
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#define MAX_IRQ_SOURCES 256
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extern unsigned int def_to_bigsmp;
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#else /* CONFIG_X86_64: */
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#define MAX_MP_BUSSES 256
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/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
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#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
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#endif /* CONFIG_X86_64 */
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#ifdef CONFIG_EISA
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extern int mp_bus_id_to_type[MAX_MP_BUSSES];
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#endif
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extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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extern unsigned int boot_cpu_physical_apicid;
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extern u8 boot_cpu_apic_version;
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extern unsigned long mp_lapic_addr;
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#ifdef CONFIG_X86_LOCAL_APIC
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extern int smp_found_config;
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#else
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# define smp_found_config 0
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#endif
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static inline void get_smp_config(void)
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{
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x86_init.mpparse.get_smp_config(0);
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}
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static inline void early_get_smp_config(void)
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{
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x86_init.mpparse.get_smp_config(1);
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}
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static inline void find_smp_config(void)
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{
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x86_init.mpparse.find_smp_config();
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}
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#ifdef CONFIG_X86_MPPARSE
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extern void e820__memblock_alloc_reserved_mpc_new(void);
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extern int enable_update_mptable;
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extern void default_find_smp_config(void);
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extern void default_get_smp_config(unsigned int early);
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#else
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static inline void e820__memblock_alloc_reserved_mpc_new(void) { }
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#define enable_update_mptable 0
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#define default_find_smp_config x86_init_noop
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#define default_get_smp_config x86_init_uint_noop
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#endif
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int generic_processor_info(int apicid, int version);
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#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
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struct physid_mask {
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unsigned long mask[PHYSID_ARRAY_SIZE];
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};
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typedef struct physid_mask physid_mask_t;
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#define physid_set(physid, map) set_bit(physid, (map).mask)
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#define physid_clear(physid, map) clear_bit(physid, (map).mask)
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#define physid_isset(physid, map) test_bit(physid, (map).mask)
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#define physid_test_and_set(physid, map) \
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test_and_set_bit(physid, (map).mask)
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#define physids_and(dst, src1, src2) \
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bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
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#define physids_or(dst, src1, src2) \
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bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
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#define physids_clear(map) \
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bitmap_zero((map).mask, MAX_LOCAL_APIC)
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#define physids_complement(dst, src) \
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bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
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#define physids_empty(map) \
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bitmap_empty((map).mask, MAX_LOCAL_APIC)
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#define physids_equal(map1, map2) \
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bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
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#define physids_weight(map) \
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bitmap_weight((map).mask, MAX_LOCAL_APIC)
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#define physids_shift_right(d, s, n) \
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bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
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#define physids_shift_left(d, s, n) \
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bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
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static inline unsigned long physids_coerce(physid_mask_t *map)
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{
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return map->mask[0];
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}
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static inline void physids_promote(unsigned long physids, physid_mask_t *map)
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{
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physids_clear(*map);
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map->mask[0] = physids;
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}
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static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
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{
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physids_clear(*map);
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physid_set(physid, *map);
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}
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#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
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#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
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extern physid_mask_t phys_cpu_present_map;
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#endif /* _ASM_X86_MPSPEC_H */
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