/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MICROCODE_H
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#define _ASM_X86_MICROCODE_H
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#include <asm/cpu.h>
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#include <linux/earlycpio.h>
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#include <linux/initrd.h>
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#include <asm/microcode_amd.h>
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struct ucode_patch {
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struct list_head plist;
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void *data; /* Intel uses only this one */
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unsigned int size;
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u32 patch_id;
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u16 equiv_cpu;
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};
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extern struct list_head microcode_cache;
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struct cpu_signature {
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unsigned int sig;
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unsigned int pf;
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unsigned int rev;
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};
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struct device;
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enum ucode_state {
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UCODE_OK = 0,
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UCODE_NEW,
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UCODE_UPDATED,
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UCODE_NFOUND,
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UCODE_ERROR,
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};
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struct microcode_ops {
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enum ucode_state (*request_microcode_user) (int cpu,
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const void __user *buf, size_t size);
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enum ucode_state (*request_microcode_fw) (int cpu, struct device *,
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bool refresh_fw);
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void (*microcode_fini_cpu) (int cpu);
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/*
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* The generic 'microcode_core' part guarantees that
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* the callbacks below run on a target cpu when they
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* are being called.
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* See also the "Synchronization" section in microcode_core.c.
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*/
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enum ucode_state (*apply_microcode) (int cpu);
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int (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
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};
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struct ucode_cpu_info {
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struct cpu_signature cpu_sig;
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int valid;
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void *mc;
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};
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extern struct ucode_cpu_info ucode_cpu_info[];
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struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa);
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#ifdef CONFIG_MICROCODE_INTEL
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extern struct microcode_ops * __init init_intel_microcode(void);
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#else
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static inline struct microcode_ops * __init init_intel_microcode(void)
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{
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return NULL;
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}
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#endif /* CONFIG_MICROCODE_INTEL */
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#ifdef CONFIG_MICROCODE_AMD
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extern struct microcode_ops * __init init_amd_microcode(void);
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extern void __exit exit_amd_microcode(void);
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#else
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static inline struct microcode_ops * __init init_amd_microcode(void)
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{
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return NULL;
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}
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static inline void __exit exit_amd_microcode(void) {}
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#endif
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#define MAX_UCODE_COUNT 128
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#define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
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#define CPUID_INTEL1 QCHAR('G', 'e', 'n', 'u')
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#define CPUID_INTEL2 QCHAR('i', 'n', 'e', 'I')
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#define CPUID_INTEL3 QCHAR('n', 't', 'e', 'l')
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#define CPUID_AMD1 QCHAR('A', 'u', 't', 'h')
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#define CPUID_AMD2 QCHAR('e', 'n', 't', 'i')
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#define CPUID_AMD3 QCHAR('c', 'A', 'M', 'D')
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#define CPUID_IS(a, b, c, ebx, ecx, edx) \
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(!((ebx ^ (a))|(edx ^ (b))|(ecx ^ (c))))
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/*
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* In early loading microcode phase on BSP, boot_cpu_data is not set up yet.
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* x86_cpuid_vendor() gets vendor id for BSP.
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*
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* In 32 bit AP case, accessing boot_cpu_data needs linear address. To simplify
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* coding, we still use x86_cpuid_vendor() to get vendor id for AP.
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*
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* x86_cpuid_vendor() gets vendor information directly from CPUID.
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*/
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static inline int x86_cpuid_vendor(void)
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{
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u32 eax = 0x00000000;
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u32 ebx, ecx = 0, edx;
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native_cpuid(&eax, &ebx, &ecx, &edx);
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if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
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return X86_VENDOR_INTEL;
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if (CPUID_IS(CPUID_AMD1, CPUID_AMD2, CPUID_AMD3, ebx, ecx, edx))
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return X86_VENDOR_AMD;
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return X86_VENDOR_UNKNOWN;
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}
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static inline unsigned int x86_cpuid_family(void)
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{
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u32 eax = 0x00000001;
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u32 ebx, ecx = 0, edx;
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native_cpuid(&eax, &ebx, &ecx, &edx);
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return x86_family(eax);
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}
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#ifdef CONFIG_MICROCODE
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int __init microcode_init(void);
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extern void __init load_ucode_bsp(void);
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extern void load_ucode_ap(void);
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void reload_early_microcode(unsigned int cpu);
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extern bool get_builtin_firmware(struct cpio_data *cd, const char *name);
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extern bool initrd_gone;
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void microcode_bsp_resume(void);
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#else
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static inline int __init microcode_init(void) { return 0; };
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static inline void __init load_ucode_bsp(void) { }
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static inline void load_ucode_ap(void) { }
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static inline void reload_early_microcode(unsigned int cpu) { }
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static inline void microcode_bsp_resume(void) { }
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static inline bool
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get_builtin_firmware(struct cpio_data *cd, const char *name) { return false; }
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#endif
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#endif /* _ASM_X86_MICROCODE_H */
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