/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* intel-mid.h: Intel MID specific setup code
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*
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* (C) Copyright 2009 Intel Corporation
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*/
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#ifndef _ASM_X86_INTEL_MID_H
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#define _ASM_X86_INTEL_MID_H
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#include <linux/sfi.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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extern int intel_mid_pci_init(void);
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extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
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extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev);
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extern void intel_mid_pwr_power_off(void);
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#define INTEL_MID_PWR_LSS_OFFSET 4
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#define INTEL_MID_PWR_LSS_TYPE (1 << 7)
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extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
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extern int get_gpio_by_name(const char *name);
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extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
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extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
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extern int sfi_mrtc_num;
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extern struct sfi_rtc_table_entry sfi_mrtc_array[];
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/*
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* Here defines the array of devices platform data that IAFW would export
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* through SFI "DEVS" table, we use name and type to match the device and
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* its platform data.
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*/
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struct devs_id {
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char name[SFI_NAME_LEN + 1];
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u8 type;
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u8 delay;
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u8 msic;
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void *(*get_platform_data)(void *info);
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};
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#define sfi_device(i) \
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static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
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__section(".x86_intel_mid_dev.init") = &i
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/**
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* struct mid_sd_board_info - template for SD device creation
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* @name: identifies the driver
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* @bus_num: board-specific identifier for a given SD controller
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* @max_clk: the maximum frequency device supports
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* @platform_data: the particular data stored there is driver-specific
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*/
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struct mid_sd_board_info {
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char name[SFI_NAME_LEN];
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int bus_num;
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unsigned short addr;
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u32 max_clk;
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void *platform_data;
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};
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/*
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* Medfield is the follow-up of Moorestown, it combines two chip solution into
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* one. Other than that it also added always-on and constant tsc and lapic
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* timers. Medfield is the platform name, and the chip name is called Penwell
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* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
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* identified via MSRs.
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*/
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enum intel_mid_cpu_type {
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/* 1 was Moorestown */
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INTEL_MID_CPU_CHIP_PENWELL = 2,
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INTEL_MID_CPU_CHIP_CLOVERVIEW,
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INTEL_MID_CPU_CHIP_TANGIER,
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};
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extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
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#ifdef CONFIG_X86_INTEL_MID
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static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
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{
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return __intel_mid_cpu_chip;
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}
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static inline bool intel_mid_has_msic(void)
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{
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return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
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}
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extern void intel_scu_devices_create(void);
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extern void intel_scu_devices_destroy(void);
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#else /* !CONFIG_X86_INTEL_MID */
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#define intel_mid_identify_cpu() 0
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#define intel_mid_has_msic() 0
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static inline void intel_scu_devices_create(void) { }
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static inline void intel_scu_devices_destroy(void) { }
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#endif /* !CONFIG_X86_INTEL_MID */
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enum intel_mid_timer_options {
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INTEL_MID_TIMER_DEFAULT,
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INTEL_MID_TIMER_APBT_ONLY,
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INTEL_MID_TIMER_LAPIC_APBT,
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};
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extern enum intel_mid_timer_options intel_mid_timer_options;
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/* Bus Select SoC Fuse value */
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#define BSEL_SOC_FUSE_MASK 0x7
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/* FSB 133MHz */
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#define BSEL_SOC_FUSE_001 0x1
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/* FSB 100MHz */
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#define BSEL_SOC_FUSE_101 0x5
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/* FSB 83MHz */
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#define BSEL_SOC_FUSE_111 0x7
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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/* VRTC timer */
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#define MRST_VRTC_MAP_SZ 1024
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/* #define MRST_VRTC_PGOFFSET 0xc00 */
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extern void intel_mid_rtc_init(void);
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/* The offset for the mapping of global gpio pin to irq */
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#define INTEL_MID_IRQ_OFFSET 0x100
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#endif /* _ASM_X86_INTEL_MID_H */
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