/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* FPU data structures:
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*/
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#ifndef _ASM_X86_FPU_H
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#define _ASM_X86_FPU_H
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/*
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* The legacy x87 FPU state format, as saved by FSAVE and
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* restored by the FRSTOR instructions:
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*/
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struct fregs_state {
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u32 cwd; /* FPU Control Word */
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u32 swd; /* FPU Status Word */
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u32 twd; /* FPU Tag Word */
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u32 fip; /* FPU IP Offset */
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u32 fcs; /* FPU IP Selector */
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u32 foo; /* FPU Operand Pointer Offset */
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u32 fos; /* FPU Operand Pointer Selector */
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/* 8*10 bytes for each FP-reg = 80 bytes: */
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u32 st_space[20];
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/* Software status information [not touched by FSAVE]: */
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u32 status;
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};
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/*
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* The legacy fx SSE/MMX FPU state format, as saved by FXSAVE and
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* restored by the FXRSTOR instructions. It's similar to the FSAVE
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* format, but differs in some areas, plus has extensions at
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* the end for the XMM registers.
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*/
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struct fxregs_state {
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u16 cwd; /* Control Word */
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u16 swd; /* Status Word */
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u16 twd; /* Tag Word */
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u16 fop; /* Last Instruction Opcode */
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union {
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struct {
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u64 rip; /* Instruction Pointer */
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u64 rdp; /* Data Pointer */
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};
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struct {
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u32 fip; /* FPU IP Offset */
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u32 fcs; /* FPU IP Selector */
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u32 foo; /* FPU Operand Offset */
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u32 fos; /* FPU Operand Selector */
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};
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};
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u32 mxcsr; /* MXCSR Register State */
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u32 mxcsr_mask; /* MXCSR Mask */
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/* 8*16 bytes for each FP-reg = 128 bytes: */
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u32 st_space[32];
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/* 16*16 bytes for each XMM-reg = 256 bytes: */
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u32 xmm_space[64];
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u32 padding[12];
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union {
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u32 padding1[12];
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u32 sw_reserved[12];
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};
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} __attribute__((aligned(16)));
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/* Default value for fxregs_state.mxcsr: */
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#define MXCSR_DEFAULT 0x1f80
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/* Copy both mxcsr & mxcsr_flags with a single u64 memcpy: */
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#define MXCSR_AND_FLAGS_SIZE sizeof(u64)
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/*
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* Software based FPU emulation state. This is arbitrary really,
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* it matches the x87 format to make it easier to understand:
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*/
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struct swregs_state {
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u32 cwd;
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u32 swd;
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u32 twd;
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u32 fip;
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u32 fcs;
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u32 foo;
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u32 fos;
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/* 8*10 bytes for each FP-reg = 80 bytes: */
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u32 st_space[20];
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u8 ftop;
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u8 changed;
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u8 lookahead;
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u8 no_update;
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u8 rm;
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u8 alimit;
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struct math_emu_info *info;
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u32 entry_eip;
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};
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/*
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* List of XSAVE features Linux knows about:
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*/
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enum xfeature {
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XFEATURE_FP,
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XFEATURE_SSE,
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/*
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* Values above here are "legacy states".
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* Those below are "extended states".
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*/
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XFEATURE_YMM,
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XFEATURE_BNDREGS,
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XFEATURE_BNDCSR,
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XFEATURE_OPMASK,
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XFEATURE_ZMM_Hi256,
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XFEATURE_Hi16_ZMM,
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XFEATURE_PT_UNIMPLEMENTED_SO_FAR,
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XFEATURE_PKRU,
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XFEATURE_PASID,
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XFEATURE_RSRVD_COMP_11,
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XFEATURE_RSRVD_COMP_12,
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XFEATURE_RSRVD_COMP_13,
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XFEATURE_RSRVD_COMP_14,
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XFEATURE_LBR,
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XFEATURE_MAX,
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};
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#define XFEATURE_MASK_FP (1 << XFEATURE_FP)
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#define XFEATURE_MASK_SSE (1 << XFEATURE_SSE)
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#define XFEATURE_MASK_YMM (1 << XFEATURE_YMM)
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#define XFEATURE_MASK_BNDREGS (1 << XFEATURE_BNDREGS)
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#define XFEATURE_MASK_BNDCSR (1 << XFEATURE_BNDCSR)
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#define XFEATURE_MASK_OPMASK (1 << XFEATURE_OPMASK)
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#define XFEATURE_MASK_ZMM_Hi256 (1 << XFEATURE_ZMM_Hi256)
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#define XFEATURE_MASK_Hi16_ZMM (1 << XFEATURE_Hi16_ZMM)
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#define XFEATURE_MASK_PT (1 << XFEATURE_PT_UNIMPLEMENTED_SO_FAR)
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#define XFEATURE_MASK_PKRU (1 << XFEATURE_PKRU)
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#define XFEATURE_MASK_PASID (1 << XFEATURE_PASID)
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#define XFEATURE_MASK_LBR (1 << XFEATURE_LBR)
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#define XFEATURE_MASK_FPSSE (XFEATURE_MASK_FP | XFEATURE_MASK_SSE)
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#define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK \
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| XFEATURE_MASK_ZMM_Hi256 \
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| XFEATURE_MASK_Hi16_ZMM)
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#define FIRST_EXTENDED_XFEATURE XFEATURE_YMM
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struct reg_128_bit {
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u8 regbytes[128/8];
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};
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struct reg_256_bit {
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u8 regbytes[256/8];
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};
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struct reg_512_bit {
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u8 regbytes[512/8];
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};
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/*
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* State component 2:
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*
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* There are 16x 256-bit AVX registers named YMM0-YMM15.
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* The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
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* and are stored in 'struct fxregs_state::xmm_space[]' in the
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* "legacy" area.
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*
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* The high 128 bits are stored here.
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*/
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struct ymmh_struct {
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struct reg_128_bit hi_ymm[16];
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} __packed;
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/* Intel MPX support: */
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struct mpx_bndreg {
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u64 lower_bound;
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u64 upper_bound;
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} __packed;
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/*
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* State component 3 is used for the 4 128-bit bounds registers
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*/
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struct mpx_bndreg_state {
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struct mpx_bndreg bndreg[4];
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} __packed;
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/*
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* State component 4 is used for the 64-bit user-mode MPX
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* configuration register BNDCFGU and the 64-bit MPX status
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* register BNDSTATUS. We call the pair "BNDCSR".
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*/
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struct mpx_bndcsr {
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u64 bndcfgu;
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u64 bndstatus;
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} __packed;
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/*
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* The BNDCSR state is padded out to be 64-bytes in size.
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*/
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struct mpx_bndcsr_state {
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union {
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struct mpx_bndcsr bndcsr;
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u8 pad_to_64_bytes[64];
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};
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} __packed;
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/* AVX-512 Components: */
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/*
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* State component 5 is used for the 8 64-bit opmask registers
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* k0-k7 (opmask state).
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*/
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struct avx_512_opmask_state {
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u64 opmask_reg[8];
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} __packed;
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/*
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* State component 6 is used for the upper 256 bits of the
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* registers ZMM0-ZMM15. These 16 256-bit values are denoted
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* ZMM0_H-ZMM15_H (ZMM_Hi256 state).
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*/
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struct avx_512_zmm_uppers_state {
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struct reg_256_bit zmm_upper[16];
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} __packed;
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/*
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* State component 7 is used for the 16 512-bit registers
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* ZMM16-ZMM31 (Hi16_ZMM state).
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*/
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struct avx_512_hi16_state {
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struct reg_512_bit hi16_zmm[16];
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} __packed;
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/*
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* State component 9: 32-bit PKRU register. The state is
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* 8 bytes long but only 4 bytes is used currently.
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*/
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struct pkru_state {
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u32 pkru;
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u32 pad;
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} __packed;
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/*
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* State component 15: Architectural LBR configuration state.
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* The size of Arch LBR state depends on the number of LBRs (lbr_depth).
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*/
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struct lbr_entry {
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u64 from;
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u64 to;
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u64 info;
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};
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struct arch_lbr_state {
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u64 lbr_ctl;
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u64 lbr_depth;
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u64 ler_from;
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u64 ler_to;
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u64 ler_info;
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struct lbr_entry entries[];
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} __packed;
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/*
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* State component 10 is supervisor state used for context-switching the
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* PASID state.
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*/
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struct ia32_pasid_state {
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u64 pasid;
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} __packed;
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struct xstate_header {
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u64 xfeatures;
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u64 xcomp_bv;
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u64 reserved[6];
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} __attribute__((packed));
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/*
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* xstate_header.xcomp_bv[63] indicates that the extended_state_area
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* is in compacted format.
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*/
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#define XCOMP_BV_COMPACTED_FORMAT ((u64)1 << 63)
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/*
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* This is our most modern FPU state format, as saved by the XSAVE
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* and restored by the XRSTOR instructions.
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*
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* It consists of a legacy fxregs portion, an xstate header and
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* subsequent areas as defined by the xstate header. Not all CPUs
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* support all the extensions, so the size of the extended area
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* can vary quite a bit between CPUs.
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*/
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struct xregs_state {
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struct fxregs_state i387;
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struct xstate_header header;
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u8 extended_state_area[0];
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} __attribute__ ((packed, aligned (64)));
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/*
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* This is a union of all the possible FPU state formats
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* put together, so that we can pick the right one runtime.
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*
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* The size of the structure is determined by the largest
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* member - which is the xsave area. The padding is there
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* to ensure that statically-allocated task_structs (just
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* the init_task today) have enough space.
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*/
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union fpregs_state {
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struct fregs_state fsave;
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struct fxregs_state fxsave;
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struct swregs_state soft;
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struct xregs_state xsave;
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u8 __padding[PAGE_SIZE];
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};
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/*
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* Highest level per task FPU state data structure that
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* contains the FPU register state plus various FPU
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* state fields:
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*/
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struct fpu {
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/*
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* @last_cpu:
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*
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* Records the last CPU on which this context was loaded into
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* FPU registers. (In the lazy-restore case we might be
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* able to reuse FPU registers across multiple context switches
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* this way, if no intermediate task used the FPU.)
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*
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* A value of -1 is used to indicate that the FPU state in context
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* memory is newer than the FPU state in registers, and that the
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* FPU state should be reloaded next time the task is run.
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*/
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unsigned int last_cpu;
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/*
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* @avx512_timestamp:
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*
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* Records the timestamp of AVX512 use during last context switch.
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*/
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unsigned long avx512_timestamp;
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/*
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* @state:
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*
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* In-memory copy of all FPU registers that we save/restore
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* over context switches. If the task is using the FPU then
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* the registers in the FPU are more recent than this state
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* copy. If the task context-switches away then they get
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* saved here and represent the FPU state.
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*/
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union fpregs_state state;
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/*
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* WARNING: 'state' is dynamically-sized. Do not put
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* anything after it here.
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*/
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};
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#endif /* _ASM_X86_FPU_H */
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