/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef _ASM_X86_FPU_INTERNAL_H
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#define _ASM_X86_FPU_INTERNAL_H
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#include <linux/compat.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <asm/user.h>
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#include <asm/fpu/api.h>
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#include <asm/fpu/xstate.h>
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#include <asm/fpu/xcr.h>
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#include <asm/cpufeature.h>
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#include <asm/trace/fpu.h>
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/*
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* High level FPU state handling functions:
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*/
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extern void fpu__prepare_read(struct fpu *fpu);
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extern void fpu__prepare_write(struct fpu *fpu);
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extern void fpu__save(struct fpu *fpu);
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extern int fpu__restore_sig(void __user *buf, int ia32_frame);
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extern void fpu__drop(struct fpu *fpu);
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extern int fpu__copy(struct task_struct *dst, struct task_struct *src);
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extern void fpu__clear_user_states(struct fpu *fpu);
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extern void fpu__clear_all(struct fpu *fpu);
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extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
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/*
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* Boot time FPU initialization functions:
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*/
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extern void fpu__init_cpu(void);
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extern void fpu__init_system_xstate(void);
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extern void fpu__init_cpu_xstate(void);
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extern void fpu__init_system(void);
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extern void fpu__init_check_bugs(void);
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extern void fpu__resume_cpu(void);
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extern u64 fpu__get_supported_xfeatures_mask(void);
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/*
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* Debugging facility:
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*/
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#ifdef CONFIG_X86_DEBUG_FPU
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# define WARN_ON_FPU(x) WARN_ON_ONCE(x)
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#else
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# define WARN_ON_FPU(x) ({ (void)(x); 0; })
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#endif
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/*
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* FPU related CPU feature flag helper routines:
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*/
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static __always_inline __pure bool use_xsaveopt(void)
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{
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return static_cpu_has(X86_FEATURE_XSAVEOPT);
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}
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static __always_inline __pure bool use_xsave(void)
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{
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return static_cpu_has(X86_FEATURE_XSAVE);
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}
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static __always_inline __pure bool use_fxsr(void)
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{
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return static_cpu_has(X86_FEATURE_FXSR);
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}
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/*
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* fpstate handling functions:
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*/
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extern union fpregs_state init_fpstate;
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extern void fpstate_init(union fpregs_state *state);
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#ifdef CONFIG_MATH_EMULATION
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extern void fpstate_init_soft(struct swregs_state *soft);
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#else
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static inline void fpstate_init_soft(struct swregs_state *soft) {}
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#endif
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static inline void fpstate_init_xstate(struct xregs_state *xsave)
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{
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/*
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* XRSTORS requires these bits set in xcomp_bv, or it will
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* trigger #GP:
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*/
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xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask_all;
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}
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static inline void fpstate_init_fxstate(struct fxregs_state *fx)
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{
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fx->cwd = 0x37f;
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fx->mxcsr = MXCSR_DEFAULT;
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}
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extern void fpstate_sanitize_xstate(struct fpu *fpu);
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/* Returns 0 or the negated trap number, which results in -EFAULT for #PF */
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#define user_insn(insn, output, input...) \
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({ \
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int err; \
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\
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might_fault(); \
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\
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asm volatile(ASM_STAC "\n" \
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"1: " #insn "\n" \
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"2: " ASM_CLAC "\n" \
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".section .fixup,\"ax\"\n" \
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"3: negl %%eax\n" \
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" jmp 2b\n" \
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".previous\n" \
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_ASM_EXTABLE_FAULT(1b, 3b) \
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: [err] "=a" (err), output \
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: "0"(0), input); \
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err; \
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})
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#define kernel_insn_err(insn, output, input...) \
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({ \
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int err; \
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asm volatile("1:" #insn "\n\t" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl $-1,%[err]\n" \
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" jmp 2b\n" \
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".previous\n" \
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_ASM_EXTABLE(1b, 3b) \
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: [err] "=r" (err), output \
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: "0"(0), input); \
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err; \
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})
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#define kernel_insn(insn, output, input...) \
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asm volatile("1:" #insn "\n\t" \
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"2:\n" \
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_ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore) \
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: output : input)
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static inline int copy_fregs_to_user(struct fregs_state __user *fx)
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{
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return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
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}
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static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
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else
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return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
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}
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static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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else
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kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline int copy_kernel_to_fxregs_err(struct fxregs_state *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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return kernel_insn_err(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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else
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return kernel_insn_err(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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else
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return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline void copy_kernel_to_fregs(struct fregs_state *fx)
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{
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kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline int copy_kernel_to_fregs_err(struct fregs_state *fx)
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{
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return kernel_insn_err(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline int copy_user_to_fregs(struct fregs_state __user *fx)
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{
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return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
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}
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static inline void copy_fxregs_to_kernel(struct fpu *fpu)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
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else
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asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
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}
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static inline void fxsave(struct fxregs_state *fx)
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{
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if (IS_ENABLED(CONFIG_X86_32))
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asm volatile( "fxsave %[fx]" : [fx] "=m" (*fx));
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else
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asm volatile("fxsaveq %[fx]" : [fx] "=m" (*fx));
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}
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/* These macros all use (%edi)/(%rdi) as the single memory argument. */
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#define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
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#define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
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#define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
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#define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
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#define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
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/*
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* After this @err contains 0 on success or the negated trap number when
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* the operation raises an exception. For faults this results in -EFAULT.
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*/
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#define XSTATE_OP(op, st, lmask, hmask, err) \
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asm volatile("1:" op "\n\t" \
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"xor %[err], %[err]\n" \
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"2:\n\t" \
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".pushsection .fixup,\"ax\"\n\t" \
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"3: negl %%eax\n\t" \
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"jmp 2b\n\t" \
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".popsection\n\t" \
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_ASM_EXTABLE_FAULT(1b, 3b) \
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: [err] "=a" (err) \
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: "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
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: "memory")
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/*
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* If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
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* format and supervisor states in addition to modified optimization in
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* XSAVEOPT.
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*
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* Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
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* supports modified optimization which is not supported by XSAVE.
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*
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* We use XSAVE as a fallback.
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*
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* The 661 label is defined in the ALTERNATIVE* macros as the address of the
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* original instruction which gets replaced. We need to use it here as the
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* address of the instruction where we might get an exception at.
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*/
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#define XSTATE_XSAVE(st, lmask, hmask, err) \
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asm volatile(ALTERNATIVE_2(XSAVE, \
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XSAVEOPT, X86_FEATURE_XSAVEOPT, \
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XSAVES, X86_FEATURE_XSAVES) \
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"\n" \
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"xor %[err], %[err]\n" \
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"3:\n" \
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".pushsection .fixup,\"ax\"\n" \
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"4: movl $-2, %[err]\n" \
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"jmp 3b\n" \
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".popsection\n" \
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_ASM_EXTABLE(661b, 4b) \
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: [err] "=r" (err) \
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: "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
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: "memory")
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/*
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* Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
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* XSAVE area format.
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*/
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#define XSTATE_XRESTORE(st, lmask, hmask) \
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asm volatile(ALTERNATIVE(XRSTOR, \
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XRSTORS, X86_FEATURE_XSAVES) \
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"\n" \
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"3:\n" \
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_ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\
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: \
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: "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
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: "memory")
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/*
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* This function is called only during boot time when x86 caps are not set
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* up and alternative can not be used yet.
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*/
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static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate)
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{
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u64 mask = -1;
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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WARN_ON(system_state != SYSTEM_BOOTING);
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if (boot_cpu_has(X86_FEATURE_XSAVES))
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XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
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else
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XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
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/*
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* We should never fault when copying from a kernel buffer, and the FPU
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* state we set at boot time should be valid.
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*/
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WARN_ON_FPU(err);
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}
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/*
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* Save processor xstate to xsave area.
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*/
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static inline void copy_xregs_to_kernel(struct xregs_state *xstate)
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{
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u64 mask = xfeatures_mask_all;
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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WARN_ON_FPU(!alternatives_patched);
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XSTATE_XSAVE(xstate, lmask, hmask, err);
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/* We should never fault when copying to a kernel buffer: */
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WARN_ON_FPU(err);
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}
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/*
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* Restore processor xstate from xsave area.
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*/
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static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask)
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{
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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XSTATE_XRESTORE(xstate, lmask, hmask);
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}
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/*
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* Save xstate to user space xsave area.
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*
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* We don't use modified optimization because xrstor/xrstors might track
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* a different application.
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*
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* We don't use compacted format xsave area for
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* backward compatibility for old applications which don't understand
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* compacted format of xsave area.
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*/
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static inline int copy_xregs_to_user(struct xregs_state __user *buf)
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{
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u64 mask = xfeatures_mask_user();
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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/*
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* Clear the xsave header first, so that reserved fields are
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* initialized to zero.
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*/
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err = __clear_user(&buf->header, sizeof(buf->header));
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if (unlikely(err))
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return -EFAULT;
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stac();
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XSTATE_OP(XSAVE, buf, lmask, hmask, err);
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clac();
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return err;
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}
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/*
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* Restore xstate from user space xsave area.
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*/
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static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask)
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{
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struct xregs_state *xstate = ((__force struct xregs_state *)buf);
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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stac();
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XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
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clac();
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return err;
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}
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/*
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* Restore xstate from kernel space xsave area, return an error code instead of
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* an exception.
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*/
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static inline int copy_kernel_to_xregs_err(struct xregs_state *xstate, u64 mask)
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{
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u32 lmask = mask;
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u32 hmask = mask >> 32;
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int err;
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if (static_cpu_has(X86_FEATURE_XSAVES))
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XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
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else
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XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
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return err;
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}
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extern int copy_fpregs_to_fpstate(struct fpu *fpu);
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static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask)
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{
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if (use_xsave()) {
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copy_kernel_to_xregs(&fpstate->xsave, mask);
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} else {
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if (use_fxsr())
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copy_kernel_to_fxregs(&fpstate->fxsave);
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else
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copy_kernel_to_fregs(&fpstate->fsave);
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}
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}
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static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
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{
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/*
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* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
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* pending. Clear the x87 state here by setting it to fixed values.
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* "m" is a random variable that should be in L1.
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*/
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if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) {
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asm volatile(
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"fnclex\n\t"
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"emms\n\t"
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"fildl %P[addr]" /* set F?P to defined value */
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: : [addr] "m" (fpstate));
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}
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__copy_kernel_to_fpregs(fpstate, -1);
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}
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extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
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/*
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* FPU context switch related helper methods:
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*/
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DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
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/*
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* The in-register FPU state for an FPU context on a CPU is assumed to be
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* valid if the fpu->last_cpu matches the CPU, and the fpu_fpregs_owner_ctx
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* matches the FPU.
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*
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* If the FPU register state is valid, the kernel can skip restoring the
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* FPU state from memory.
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*
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* Any code that clobbers the FPU registers or updates the in-memory
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* FPU state for a task MUST let the rest of the kernel know that the
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* FPU registers are no longer valid for this task.
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*
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* Either one of these invalidation functions is enough. Invalidate
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* a resource you control: CPU if using the CPU for something else
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* (with preemption disabled), FPU for the current task, or a task that
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* is prevented from running by the current task.
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*/
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static inline void __cpu_invalidate_fpregs_state(void)
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{
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__this_cpu_write(fpu_fpregs_owner_ctx, NULL);
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}
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static inline void __fpu_invalidate_fpregs_state(struct fpu *fpu)
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{
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fpu->last_cpu = -1;
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}
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static inline int fpregs_state_valid(struct fpu *fpu, unsigned int cpu)
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{
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return fpu == this_cpu_read(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
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}
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/*
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* These generally need preemption protection to work,
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* do try to avoid using these on their own:
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*/
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static inline void fpregs_deactivate(struct fpu *fpu)
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{
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this_cpu_write(fpu_fpregs_owner_ctx, NULL);
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trace_x86_fpu_regs_deactivated(fpu);
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}
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static inline void fpregs_activate(struct fpu *fpu)
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{
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this_cpu_write(fpu_fpregs_owner_ctx, fpu);
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trace_x86_fpu_regs_activated(fpu);
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}
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/*
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* Internal helper, do not use directly. Use switch_fpu_return() instead.
|
*/
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static inline void __fpregs_load_activate(void)
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{
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struct fpu *fpu = ¤t->thread.fpu;
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int cpu = smp_processor_id();
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if (WARN_ON_ONCE(current->flags & PF_KTHREAD))
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return;
|
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if (!fpregs_state_valid(fpu, cpu)) {
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copy_kernel_to_fpregs(&fpu->state);
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fpregs_activate(fpu);
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fpu->last_cpu = cpu;
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}
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clear_thread_flag(TIF_NEED_FPU_LOAD);
|
}
|
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/*
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* FPU state switching for scheduling.
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*
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* This is a two-stage process:
|
*
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* - switch_fpu_prepare() saves the old state.
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* This is done within the context of the old process.
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*
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* - switch_fpu_finish() sets TIF_NEED_FPU_LOAD; the floating point state
|
* will get loaded on return to userspace, or when the kernel needs it.
|
*
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* If TIF_NEED_FPU_LOAD is cleared then the CPU's FPU registers
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* are saved in the current thread's FPU register state.
|
*
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* If TIF_NEED_FPU_LOAD is set then CPU's FPU registers may not
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* hold current()'s FPU registers. It is required to load the
|
* registers before returning to userland or using the content
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* otherwise.
|
*
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* The FPU context is only stored/restored for a user task and
|
* PF_KTHREAD is used to distinguish between kernel and user threads.
|
*/
|
static inline void switch_fpu_prepare(struct task_struct *prev, int cpu)
|
{
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struct fpu *old_fpu = &prev->thread.fpu;
|
|
if (static_cpu_has(X86_FEATURE_FPU) && !(prev->flags & PF_KTHREAD)) {
|
if (!copy_fpregs_to_fpstate(old_fpu))
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old_fpu->last_cpu = -1;
|
else
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old_fpu->last_cpu = cpu;
|
|
/* But leave fpu_fpregs_owner_ctx! */
|
trace_x86_fpu_regs_deactivated(old_fpu);
|
}
|
}
|
|
/*
|
* Misc helper functions:
|
*/
|
|
/*
|
* Load PKRU from the FPU context if available. Delay loading of the
|
* complete FPU state until the return to userland.
|
*/
|
static inline void switch_fpu_finish(struct task_struct *next)
|
{
|
u32 pkru_val = init_pkru_value;
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struct pkru_state *pk;
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struct fpu *next_fpu = &next->thread.fpu;
|
|
if (!static_cpu_has(X86_FEATURE_FPU))
|
return;
|
|
set_thread_flag(TIF_NEED_FPU_LOAD);
|
|
if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
|
return;
|
|
/*
|
* PKRU state is switched eagerly because it needs to be valid before we
|
* return to userland e.g. for a copy_to_user() operation.
|
*/
|
if (!(next->flags & PF_KTHREAD)) {
|
/*
|
* If the PKRU bit in xsave.header.xfeatures is not set,
|
* then the PKRU component was in init state, which means
|
* XRSTOR will set PKRU to 0. If the bit is not set then
|
* get_xsave_addr() will return NULL because the PKRU value
|
* in memory is not valid. This means pkru_val has to be
|
* set to 0 and not to init_pkru_value.
|
*/
|
pk = get_xsave_addr(&next_fpu->state.xsave, XFEATURE_PKRU);
|
pkru_val = pk ? pk->pkru : 0;
|
}
|
__write_pkru(pkru_val);
|
}
|
|
#endif /* _ASM_X86_FPU_INTERNAL_H */
|
