/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_DEBUGREG_H
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#define _ASM_X86_DEBUGREG_H
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#include <linux/bug.h>
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#include <uapi/asm/debugreg.h>
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DECLARE_PER_CPU(unsigned long, cpu_dr7);
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#ifndef CONFIG_PARAVIRT_XXL
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/*
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* These special macros can be used to get or set a debugging register
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*/
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#define get_debugreg(var, register) \
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(var) = native_get_debugreg(register)
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#define set_debugreg(value, register) \
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native_set_debugreg(register, value)
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#endif
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static __always_inline unsigned long native_get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("mov %%db0, %0" :"=r" (val));
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break;
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case 1:
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asm("mov %%db1, %0" :"=r" (val));
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break;
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case 2:
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asm("mov %%db2, %0" :"=r" (val));
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break;
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case 3:
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asm("mov %%db3, %0" :"=r" (val));
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break;
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case 6:
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asm("mov %%db6, %0" :"=r" (val));
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break;
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case 7:
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/*
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* Apply __FORCE_ORDER to DR7 reads to forbid re-ordering them
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* with other code.
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*
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* This is needed because a DR7 access can cause a #VC exception
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* when running under SEV-ES. Taking a #VC exception is not a
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* safe thing to do just anywhere in the entry code and
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* re-ordering might place the access into an unsafe location.
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*
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* This happened in the NMI handler, where the DR7 read was
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* re-ordered to happen before the call to sev_es_ist_enter(),
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* causing stack recursion.
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*/
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asm volatile("mov %%db7, %0" : "=r" (val) : __FORCE_ORDER);
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break;
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default:
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BUG();
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}
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return val;
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}
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static __always_inline void native_set_debugreg(int regno, unsigned long value)
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{
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switch (regno) {
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case 0:
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asm("mov %0, %%db0" ::"r" (value));
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break;
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case 1:
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asm("mov %0, %%db1" ::"r" (value));
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break;
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case 2:
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asm("mov %0, %%db2" ::"r" (value));
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break;
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case 3:
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asm("mov %0, %%db3" ::"r" (value));
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break;
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case 6:
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asm("mov %0, %%db6" ::"r" (value));
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break;
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case 7:
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/*
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* Apply __FORCE_ORDER to DR7 writes to forbid re-ordering them
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* with other code.
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*
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* While is didn't happen with a DR7 write (see the DR7 read
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* comment above which explains where it happened), add the
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* __FORCE_ORDER here too to avoid similar problems in the
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* future.
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*/
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asm volatile("mov %0, %%db7" ::"r" (value), __FORCE_ORDER);
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break;
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default:
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BUG();
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}
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}
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static inline void hw_breakpoint_disable(void)
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{
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/* Zero the control register for HW Breakpoint */
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set_debugreg(0UL, 7);
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/* Zero-out the individual HW breakpoint address registers */
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set_debugreg(0UL, 0);
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set_debugreg(0UL, 1);
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set_debugreg(0UL, 2);
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set_debugreg(0UL, 3);
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}
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static __always_inline bool hw_breakpoint_active(void)
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{
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return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
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}
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extern void hw_breakpoint_restore(void);
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static __always_inline unsigned long local_db_save(void)
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{
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unsigned long dr7;
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if (static_cpu_has(X86_FEATURE_HYPERVISOR) && !hw_breakpoint_active())
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return 0;
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get_debugreg(dr7, 7);
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dr7 &= ~0x400; /* architecturally set bit */
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if (dr7)
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set_debugreg(0, 7);
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/*
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* Ensure the compiler doesn't lower the above statements into
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* the critical section; disabling breakpoints late would not
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* be good.
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*/
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barrier();
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return dr7;
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}
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static __always_inline void local_db_restore(unsigned long dr7)
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{
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/*
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* Ensure the compiler doesn't raise this statement into
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* the critical section; enabling breakpoints early would
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* not be good.
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*/
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barrier();
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if (dr7)
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set_debugreg(dr7, 7);
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}
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#ifdef CONFIG_CPU_SUP_AMD
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extern void set_dr_addr_mask(unsigned long mask, int dr);
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#else
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static inline void set_dr_addr_mask(unsigned long mask, int dr) { }
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#endif
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#endif /* _ASM_X86_DEBUGREG_H */
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