/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* X86 specific ACPICA environments and implementation
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*
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* Copyright (C) 2014, Intel Corporation
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* Author: Lv Zheng <lv.zheng@intel.com>
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*/
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#ifndef _ASM_X86_ACENV_H
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#define _ASM_X86_ACENV_H
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#include <asm/special_insns.h>
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/* Asm macros */
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/*
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* ACPI_FLUSH_CPU_CACHE() flushes caches on entering sleep states.
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* It is required to prevent data loss.
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*
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* While running inside virtual machine, the kernel can bypass cache flushing.
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* Changing sleep state in a virtual machine doesn't affect the host system
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* sleep state and cannot lead to data loss.
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*/
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#define ACPI_FLUSH_CPU_CACHE() \
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do { \
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if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) \
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wbinvd(); \
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} while (0)
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int __acpi_acquire_global_lock(unsigned int *lock);
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int __acpi_release_global_lock(unsigned int *lock);
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#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
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((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
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#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
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((Acq) = __acpi_release_global_lock(&facs->global_lock))
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/*
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* Math helper asm macros
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*/
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#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
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asm("divl %2;" \
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: "=a"(q32), "=d"(r32) \
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: "r"(d32), \
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"0"(n_lo), "1"(n_hi))
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#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
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asm("shrl $1,%2 ;" \
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"rcrl $1,%3;" \
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: "=r"(n_hi), "=r"(n_lo) \
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: "0"(n_hi), "1"(n_lo))
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#endif /* _ASM_X86_ACENV_H */
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