* Xilinx NWL PCIe Root Port Bridge DT description
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Required properties:
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- compatible: Should contain "xlnx,nwl-pcie-2.11"
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- #address-cells: Address representation for root ports, set to <3>
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- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- reg: Should contain Bridge, PCIe Controller registers location,
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configuration space, and length
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- reg-names: Must include the following entries:
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"breg": bridge registers
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"pcireg": PCIe controller registers
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"cfg": configuration space region
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- device_type: must be "pci"
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- interrupts: Should contain NWL PCIe interrupt
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- interrupt-names: Must include the following entries:
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"msi1, msi0": interrupt asserted when an MSI is received
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"intx": interrupt asserted when a legacy interrupt is received
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"misc": interrupt asserted when miscellaneous interrupt is received
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCI interface to interrupt numbers.
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- ranges: ranges for the PCI memory regions (I/O space region is not
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supported by hardware)
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Please refer to the standard PCI bus binding document for a more
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detailed explanation
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- msi-controller: indicates that this is MSI controller node
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- msi-parent: MSI parent of the root complex itself
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- legacy-interrupt-controller: Interrupt controller device node for Legacy
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interrupts
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- interrupt-controller: identifies the node as an interrupt controller
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- #interrupt-cells: should be set to 1
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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Example:
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++++++++
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nwl_pcie: pcie@fd0e0000 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "xlnx,nwl-pcie-2.11";
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#interrupt-cells = <1>;
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msi-controller;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
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interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
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<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
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<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
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<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
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msi-parent = <&nwl_pcie>;
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reg = <0x0 0xfd0e0000 0x0 0x1000>,
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<0x0 0xfd480000 0x0 0x1000>,
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<0x80 0x00000000 0x0 0x1000000>;
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reg-names = "breg", "pcireg", "cfg";
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ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
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0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
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pcie_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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