// SPDX-License-Identifier: GPL-2.0+
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/*
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* linux/sound/soc/hisilicon/hi3660-i2s.c
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*
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* I2S IP driver for hi3660.
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*
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* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/jiffies.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/reset-controller.h>
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include "hi3660-i2s.h"
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struct hi3660_i2s {
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struct device *dev;
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struct reset_control *rc;
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int clocks;
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struct regulator *regu_asp;
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struct pinctrl *pctrl;
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struct pinctrl_state *pin_default;
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struct pinctrl_state *pin_idle;
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struct clk *asp_subsys_clk;
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struct snd_soc_dai_driver dai;
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void __iomem *base;
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void __iomem *base_syscon;
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phys_addr_t base_phys;
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struct snd_dmaengine_dai_dma_data dma_data[2];
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spinlock_t lock;
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int rate;
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int format;
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int bits;
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int channels;
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u32 master;
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u32 status;
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};
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static void update_bits(struct hi3660_i2s *i2s, u32 ofs, u32 reset, u32 set)
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{
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u32 val = readl(i2s->base + ofs) & ~reset;
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writel(val | set, i2s->base + ofs);
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}
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static void update_bits_syscon(struct hi3660_i2s *i2s,
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u32 ofs, u32 reset, u32 set)
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{
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u32 val = readl(i2s->base_syscon + ofs) & ~reset;
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writel(val | set, i2s->base_syscon + ofs);
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}
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static int enable_format(struct hi3660_i2s *i2s,
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struct snd_pcm_substream *substream)
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{
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switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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i2s->master = false;
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update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
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0, HI_ASP_CFG_R_CLK_SEL_EN);
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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i2s->master = true;
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update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
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HI_ASP_CFG_R_CLK_SEL_EN, 0);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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/* deassert reset on sio_bt*/
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update_bits_syscon(i2s, HI_ASP_CFG_R_RST_CTRLDIS_REG,
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0, BIT(2)|BIT(6)|BIT(8)|BIT(16));
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/* enable clk before frequency division */
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update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_EN_REG,
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0, BIT(5)|BIT(6));
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/* enable frequency division */
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update_bits_syscon(i2s, HI_ASP_CFG_R_GATE_CLKDIV_EN_REG,
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0, BIT(2)|BIT(5));
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/* select clk */
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update_bits_syscon(i2s, HI_ASP_CFG_R_CLK_SEL_REG,
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HI_ASP_MASK, HI_ASP_CFG_R_CLK_SEL);
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/* select clk_div */
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update_bits_syscon(i2s, HI_ASP_CFG_R_CLK1_DIV_REG,
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HI_ASP_MASK, HI_ASP_CFG_R_CLK1_DIV_SEL);
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update_bits_syscon(i2s, HI_ASP_CFG_R_CLK4_DIV_REG,
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HI_ASP_MASK, HI_ASP_CFG_R_CLK4_DIV_SEL);
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update_bits_syscon(i2s, HI_ASP_CFG_R_CLK6_DIV_REG,
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HI_ASP_MASK, HI_ASP_CFG_R_CLK6_DIV_SEL);
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/* sio config */
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update_bits(i2s, HI_ASP_SIO_MODE_REG, HI_ASP_MASK, 0x0);
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update_bits(i2s, HI_ASP_SIO_DATA_WIDTH_SET_REG, HI_ASP_MASK, 0x9);
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update_bits(i2s, HI_ASP_SIO_I2S_POS_MERGE_EN_REG, HI_ASP_MASK, 0x1);
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update_bits(i2s, HI_ASP_SIO_I2S_START_POS_REG, HI_ASP_MASK, 0x0);
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return 0;
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}
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static void shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *cpu_dai)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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if (!IS_ERR_OR_NULL(i2s->asp_subsys_clk))
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clk_disable_unprepare(i2s->asp_subsys_clk);
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}
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static void txctrl(struct snd_soc_dai *cpu_dai, int on)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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spin_lock(&i2s->lock);
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if (on) {
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/* enable SIO TX */
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update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
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HI_ASP_SIO_TX_ENABLE |
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HI_ASP_SIO_TX_DATA_MERGE |
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HI_ASP_SIO_TX_FIFO_THRESHOLD |
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HI_ASP_SIO_RX_ENABLE |
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HI_ASP_SIO_RX_DATA_MERGE |
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HI_ASP_SIO_RX_FIFO_THRESHOLD);
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} else {
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/* disable SIO TX */
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update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
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HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
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}
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spin_unlock(&i2s->lock);
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}
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static void rxctrl(struct snd_soc_dai *cpu_dai, int on)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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spin_lock(&i2s->lock);
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if (on)
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/* enable SIO RX */
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update_bits(i2s, HI_ASP_SIO_CT_SET_REG, 0,
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HI_ASP_SIO_TX_ENABLE |
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HI_ASP_SIO_TX_DATA_MERGE |
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HI_ASP_SIO_TX_FIFO_THRESHOLD |
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HI_ASP_SIO_RX_ENABLE |
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HI_ASP_SIO_RX_DATA_MERGE |
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HI_ASP_SIO_RX_FIFO_THRESHOLD);
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else
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/* disable SIO RX */
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update_bits(i2s, HI_ASP_SIO_CT_CLR_REG, 0,
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HI_ASP_SIO_TX_ENABLE | HI_ASP_SIO_RX_ENABLE);
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spin_unlock(&i2s->lock);
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}
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static int set_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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return 0;
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}
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static int set_format(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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i2s->format = fmt;
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i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
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SND_SOC_DAIFMT_CBS_CFS;
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return 0;
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}
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static int hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *cpu_dai)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
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struct snd_dmaengine_dai_dma_data *dma_data;
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dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
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enable_format(i2s, substream);
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dma_data->maxburst = 4;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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dma_data->addr = i2s->base_phys +
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HI_ASP_SIO_I2S_DUAL_TX_CHN_REG;
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else
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dma_data->addr = i2s->base_phys +
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HI_ASP_SIO_I2S_DUAL_RX_CHN_REG;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_U16_LE:
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case SNDRV_PCM_FORMAT_S16_LE:
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i2s->bits = 16;
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dma_data->addr_width = 4;
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break;
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case SNDRV_PCM_FORMAT_U24_LE:
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case SNDRV_PCM_FORMAT_S24_LE:
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i2s->bits = 32;
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dma_data->addr_width = 4;
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break;
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default:
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dev_err(cpu_dai->dev, "Bad format\n");
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return -EINVAL;
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}
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return 0;
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}
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static int trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *cpu_dai)
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{
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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rxctrl(cpu_dai, 1);
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else
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txctrl(cpu_dai, 1);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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rxctrl(cpu_dai, 0);
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else
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txctrl(cpu_dai, 0);
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break;
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default:
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dev_err(cpu_dai->dev, "unknown cmd\n");
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return -EINVAL;
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}
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return 0;
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}
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static int dai_probe(struct snd_soc_dai *dai)
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{
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struct hi3660_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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snd_soc_dai_init_dma_data(dai,
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&i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
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&i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
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return 0;
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}
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static struct snd_soc_dai_ops dai_ops = {
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.trigger = trigger,
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.hw_params = hw_params,
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.set_fmt = set_format,
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.set_sysclk = set_sysclk,
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.startup = startup,
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.shutdown = shutdown,
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};
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static struct snd_soc_dai_driver dai_init = {
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.name = "hi3660_i2s",
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.probe = dai_probe,
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_U16_LE,
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.rates = SNDRV_PCM_RATE_48000,
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},
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.capture = {
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.channels_min = 2,
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.channels_max = 2,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_U16_LE,
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.rates = SNDRV_PCM_RATE_48000,
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},
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.ops = &dai_ops,
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};
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static const struct snd_soc_component_driver component_driver = {
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.name = "hi3660_i2s",
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};
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#include <sound/dmaengine_pcm.h>
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static const struct snd_pcm_hardware sound_hardware = {
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.info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_RESUME |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_HALF_DUPLEX,
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.period_bytes_min = 4096,
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.period_bytes_max = 4096,
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.periods_min = 4,
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.periods_max = UINT_MAX,
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.buffer_bytes_max = SIZE_MAX,
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};
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static const struct snd_dmaengine_pcm_config dmaengine_pcm_config = {
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.pcm_hardware = &sound_hardware,
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.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
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.prealloc_buffer_size = 64 * 1024,
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};
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static int hi3660_i2s_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct hi3660_i2s *i2s;
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struct resource *res;
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int ret;
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i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
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if (!i2s)
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return -ENOMEM;
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i2s->dev = dev;
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spin_lock_init(&i2s->lock);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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ret = -ENODEV;
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return ret;
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}
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i2s->base_phys = (phys_addr_t)res->start;
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i2s->dai = dai_init;
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dev_set_drvdata(&pdev->dev, i2s);
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i2s->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(i2s->base)) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = PTR_ERR(i2s->base);
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return ret;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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ret = -ENODEV;
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return ret;
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}
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i2s->base_syscon = devm_ioremap(dev, res->start, resource_size(res));
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if (IS_ERR(i2s->base_syscon)) {
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dev_err(&pdev->dev, "ioremap failed\n");
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ret = PTR_ERR(i2s->base_syscon);
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return ret;
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}
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/* i2s iomux config */
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i2s->pctrl = devm_pinctrl_get(dev);
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if (IS_ERR(i2s->pctrl)) {
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dev_err(dev, "could not get pinctrl\n");
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ret = -EIO;
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return ret;
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}
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i2s->pin_default = pinctrl_lookup_state(i2s->pctrl,
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PINCTRL_STATE_DEFAULT);
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if (IS_ERR(i2s->pin_default)) {
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dev_err(dev,
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"could not get default state (%li)\n",
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PTR_ERR(i2s->pin_default));
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ret = -EIO;
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return ret;
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}
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if (pinctrl_select_state(i2s->pctrl, i2s->pin_default)) {
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dev_err(dev, "could not set pins to default state\n");
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ret = -EIO;
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return ret;
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}
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ret = devm_snd_dmaengine_pcm_register(&pdev->dev,
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&dmaengine_pcm_config, 0);
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if (ret)
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return ret;
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ret = snd_soc_register_component(&pdev->dev, &component_driver,
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&i2s->dai, 1);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register dai\n");
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return ret;
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}
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return 0;
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}
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static int hi3660_i2s_remove(struct platform_device *pdev)
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{
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struct hi3660_i2s *i2s = dev_get_drvdata(&pdev->dev);
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snd_soc_unregister_component(&pdev->dev);
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dev_set_drvdata(&pdev->dev, NULL);
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pinctrl_put(i2s->pctrl);
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return 0;
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}
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static const struct of_device_id dt_ids[] = {
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{ .compatible = "hisilicon,hi3660-i2s-1.0" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dt_ids);
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static struct platform_driver local_platform_driver = {
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.probe = hi3660_i2s_probe,
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.remove = hi3660_i2s_remove,
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.driver = {
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.name = "hi3660_i2s",
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.owner = THIS_MODULE,
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.of_match_table = dt_ids,
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},
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};
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module_platform_driver(local_platform_driver);
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MODULE_DESCRIPTION("Hisilicon I2S driver");
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MODULE_AUTHOR("Guangke Ji <j00209069@notesmail.huawei.com>");
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MODULE_LICENSE("GPL");
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