/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _GEN_PV_LOCK_SLOWPATH
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#error "do not include this file"
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#endif
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#include <linux/hash.h>
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#include <linux/memblock.h>
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#include <linux/debug_locks.h>
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/*
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* Implement paravirt qspinlocks; the general idea is to halt the vcpus instead
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* of spinning them.
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*
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* This relies on the architecture to provide two paravirt hypercalls:
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*
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* pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
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* pv_kick(cpu) -- wakes a suspended vcpu
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*
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* Using these we implement __pv_queued_spin_lock_slowpath() and
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* __pv_queued_spin_unlock() to replace native_queued_spin_lock_slowpath() and
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* native_queued_spin_unlock().
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*/
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#define _Q_SLOW_VAL (3U << _Q_LOCKED_OFFSET)
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/*
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* Queue Node Adaptive Spinning
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*
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* A queue node vCPU will stop spinning if the vCPU in the previous node is
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* not running. The one lock stealing attempt allowed at slowpath entry
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* mitigates the slight slowdown for non-overcommitted guest with this
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* aggressive wait-early mechanism.
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*
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* The status of the previous node will be checked at fixed interval
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* controlled by PV_PREV_CHECK_MASK. This is to ensure that we won't
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* pound on the cacheline of the previous node too heavily.
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*/
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#define PV_PREV_CHECK_MASK 0xff
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/*
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* Queue node uses: vcpu_running & vcpu_halted.
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* Queue head uses: vcpu_running & vcpu_hashed.
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*/
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enum vcpu_state {
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vcpu_running = 0,
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vcpu_halted, /* Used only in pv_wait_node */
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vcpu_hashed, /* = pv_hash'ed + vcpu_halted */
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};
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struct pv_node {
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struct mcs_spinlock mcs;
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int cpu;
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u8 state;
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};
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/*
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* Hybrid PV queued/unfair lock
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*
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* By replacing the regular queued_spin_trylock() with the function below,
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* it will be called once when a lock waiter enter the PV slowpath before
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* being queued.
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*
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* The pending bit is set by the queue head vCPU of the MCS wait queue in
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* pv_wait_head_or_lock() to signal that it is ready to spin on the lock.
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* When that bit becomes visible to the incoming waiters, no lock stealing
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* is allowed. The function will return immediately to make the waiters
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* enter the MCS wait queue. So lock starvation shouldn't happen as long
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* as the queued mode vCPUs are actively running to set the pending bit
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* and hence disabling lock stealing.
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*
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* When the pending bit isn't set, the lock waiters will stay in the unfair
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* mode spinning on the lock unless the MCS wait queue is empty. In this
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* case, the lock waiters will enter the queued mode slowpath trying to
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* become the queue head and set the pending bit.
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*
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* This hybrid PV queued/unfair lock combines the best attributes of a
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* queued lock (no lock starvation) and an unfair lock (good performance
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* on not heavily contended locks).
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*/
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#define queued_spin_trylock(l) pv_hybrid_queued_unfair_trylock(l)
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static inline bool pv_hybrid_queued_unfair_trylock(struct qspinlock *lock)
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{
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/*
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* Stay in unfair lock mode as long as queued mode waiters are
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* present in the MCS wait queue but the pending bit isn't set.
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*/
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for (;;) {
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int val = atomic_read(&lock->val);
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if (!(val & _Q_LOCKED_PENDING_MASK) &&
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(cmpxchg_acquire(&lock->locked, 0, _Q_LOCKED_VAL) == 0)) {
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lockevent_inc(pv_lock_stealing);
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return true;
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}
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if (!(val & _Q_TAIL_MASK) || (val & _Q_PENDING_MASK))
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break;
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cpu_relax();
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}
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return false;
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}
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/*
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* The pending bit is used by the queue head vCPU to indicate that it
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* is actively spinning on the lock and no lock stealing is allowed.
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*/
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#if _Q_PENDING_BITS == 8
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static __always_inline void set_pending(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->pending, 1);
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}
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/*
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* The pending bit check in pv_queued_spin_steal_lock() isn't a memory
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* barrier. Therefore, an atomic cmpxchg_acquire() is used to acquire the
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* lock just to be sure that it will get it.
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*/
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static __always_inline int trylock_clear_pending(struct qspinlock *lock)
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{
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return !READ_ONCE(lock->locked) &&
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(cmpxchg_acquire(&lock->locked_pending, _Q_PENDING_VAL,
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_Q_LOCKED_VAL) == _Q_PENDING_VAL);
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}
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#else /* _Q_PENDING_BITS == 8 */
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static __always_inline void set_pending(struct qspinlock *lock)
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{
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atomic_or(_Q_PENDING_VAL, &lock->val);
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}
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static __always_inline int trylock_clear_pending(struct qspinlock *lock)
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{
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int val = atomic_read(&lock->val);
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for (;;) {
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int old, new;
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if (val & _Q_LOCKED_MASK)
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break;
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/*
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* Try to clear pending bit & set locked bit
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*/
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old = val;
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new = (val & ~_Q_PENDING_MASK) | _Q_LOCKED_VAL;
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val = atomic_cmpxchg_acquire(&lock->val, old, new);
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if (val == old)
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return 1;
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}
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return 0;
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}
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#endif /* _Q_PENDING_BITS == 8 */
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/*
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* Lock and MCS node addresses hash table for fast lookup
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*
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* Hashing is done on a per-cacheline basis to minimize the need to access
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* more than one cacheline.
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*
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* Dynamically allocate a hash table big enough to hold at least 4X the
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* number of possible cpus in the system. Allocation is done on page
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* granularity. So the minimum number of hash buckets should be at least
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* 256 (64-bit) or 512 (32-bit) to fully utilize a 4k page.
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*
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* Since we should not be holding locks from NMI context (very rare indeed) the
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* max load factor is 0.75, which is around the point where open addressing
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* breaks down.
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*
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*/
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struct pv_hash_entry {
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struct qspinlock *lock;
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struct pv_node *node;
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};
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#define PV_HE_PER_LINE (SMP_CACHE_BYTES / sizeof(struct pv_hash_entry))
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#define PV_HE_MIN (PAGE_SIZE / sizeof(struct pv_hash_entry))
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static struct pv_hash_entry *pv_lock_hash;
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static unsigned int pv_lock_hash_bits __read_mostly;
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/*
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* Allocate memory for the PV qspinlock hash buckets
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*
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* This function should be called from the paravirt spinlock initialization
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* routine.
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*/
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void __init __pv_init_lock_hash(void)
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{
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int pv_hash_size = ALIGN(4 * num_possible_cpus(), PV_HE_PER_LINE);
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if (pv_hash_size < PV_HE_MIN)
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pv_hash_size = PV_HE_MIN;
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/*
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* Allocate space from bootmem which should be page-size aligned
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* and hence cacheline aligned.
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*/
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pv_lock_hash = alloc_large_system_hash("PV qspinlock",
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sizeof(struct pv_hash_entry),
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pv_hash_size, 0,
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HASH_EARLY | HASH_ZERO,
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&pv_lock_hash_bits, NULL,
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pv_hash_size, pv_hash_size);
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}
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#define for_each_hash_entry(he, offset, hash) \
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for (hash &= ~(PV_HE_PER_LINE - 1), he = &pv_lock_hash[hash], offset = 0; \
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offset < (1 << pv_lock_hash_bits); \
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offset++, he = &pv_lock_hash[(hash + offset) & ((1 << pv_lock_hash_bits) - 1)])
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static struct qspinlock **pv_hash(struct qspinlock *lock, struct pv_node *node)
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{
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unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits);
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struct pv_hash_entry *he;
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int hopcnt = 0;
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for_each_hash_entry(he, offset, hash) {
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hopcnt++;
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if (!cmpxchg(&he->lock, NULL, lock)) {
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WRITE_ONCE(he->node, node);
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lockevent_pv_hop(hopcnt);
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return &he->lock;
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}
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}
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/*
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* Hard assume there is a free entry for us.
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*
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* This is guaranteed by ensuring every blocked lock only ever consumes
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* a single entry, and since we only have 4 nesting levels per CPU
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* and allocated 4*nr_possible_cpus(), this must be so.
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*
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* The single entry is guaranteed by having the lock owner unhash
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* before it releases.
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*/
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BUG();
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}
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static struct pv_node *pv_unhash(struct qspinlock *lock)
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{
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unsigned long offset, hash = hash_ptr(lock, pv_lock_hash_bits);
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struct pv_hash_entry *he;
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struct pv_node *node;
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for_each_hash_entry(he, offset, hash) {
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if (READ_ONCE(he->lock) == lock) {
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node = READ_ONCE(he->node);
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WRITE_ONCE(he->lock, NULL);
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return node;
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}
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}
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/*
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* Hard assume we'll find an entry.
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*
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* This guarantees a limited lookup time and is itself guaranteed by
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* having the lock owner do the unhash -- IFF the unlock sees the
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* SLOW flag, there MUST be a hash entry.
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*/
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BUG();
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}
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/*
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* Return true if when it is time to check the previous node which is not
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* in a running state.
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*/
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static inline bool
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pv_wait_early(struct pv_node *prev, int loop)
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{
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if ((loop & PV_PREV_CHECK_MASK) != 0)
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return false;
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return READ_ONCE(prev->state) != vcpu_running;
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}
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/*
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* Initialize the PV part of the mcs_spinlock node.
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*/
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static void pv_init_node(struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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BUILD_BUG_ON(sizeof(struct pv_node) > sizeof(struct qnode));
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pn->cpu = smp_processor_id();
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pn->state = vcpu_running;
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}
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/*
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* Wait for node->locked to become true, halt the vcpu after a short spin.
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* pv_kick_node() is used to set _Q_SLOW_VAL and fill in hash table on its
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* behalf.
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*/
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static void pv_wait_node(struct mcs_spinlock *node, struct mcs_spinlock *prev)
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{
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struct pv_node *pn = (struct pv_node *)node;
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struct pv_node *pp = (struct pv_node *)prev;
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int loop;
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bool wait_early;
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for (;;) {
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for (wait_early = false, loop = SPIN_THRESHOLD; loop; loop--) {
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if (READ_ONCE(node->locked))
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return;
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if (pv_wait_early(pp, loop)) {
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wait_early = true;
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break;
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}
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cpu_relax();
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}
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/*
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* Order pn->state vs pn->locked thusly:
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*
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* [S] pn->state = vcpu_halted [S] next->locked = 1
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* MB MB
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* [L] pn->locked [RmW] pn->state = vcpu_hashed
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*
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* Matches the cmpxchg() from pv_kick_node().
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*/
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smp_store_mb(pn->state, vcpu_halted);
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if (!READ_ONCE(node->locked)) {
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lockevent_inc(pv_wait_node);
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lockevent_cond_inc(pv_wait_early, wait_early);
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pv_wait(&pn->state, vcpu_halted);
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}
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/*
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* If pv_kick_node() changed us to vcpu_hashed, retain that
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* value so that pv_wait_head_or_lock() knows to not also try
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* to hash this lock.
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*/
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cmpxchg(&pn->state, vcpu_halted, vcpu_running);
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/*
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* If the locked flag is still not set after wakeup, it is a
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* spurious wakeup and the vCPU should wait again. However,
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* there is a pretty high overhead for CPU halting and kicking.
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* So it is better to spin for a while in the hope that the
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* MCS lock will be released soon.
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*/
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lockevent_cond_inc(pv_spurious_wakeup,
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!READ_ONCE(node->locked));
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}
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/*
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* By now our node->locked should be 1 and our caller will not actually
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* spin-wait for it. We do however rely on our caller to do a
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* load-acquire for us.
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*/
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}
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/*
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* Called after setting next->locked = 1 when we're the lock owner.
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*
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* Instead of waking the waiters stuck in pv_wait_node() advance their state
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* such that they're waiting in pv_wait_head_or_lock(), this avoids a
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* wake/sleep cycle.
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*/
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static void pv_kick_node(struct qspinlock *lock, struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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/*
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* If the vCPU is indeed halted, advance its state to match that of
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* pv_wait_node(). If OTOH this fails, the vCPU was running and will
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* observe its next->locked value and advance itself.
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*
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* Matches with smp_store_mb() and cmpxchg() in pv_wait_node()
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*
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* The write to next->locked in arch_mcs_spin_unlock_contended()
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* must be ordered before the read of pn->state in the cmpxchg()
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* below for the code to work correctly. To guarantee full ordering
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* irrespective of the success or failure of the cmpxchg(),
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* a relaxed version with explicit barrier is used. The control
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* dependency will order the reading of pn->state before any
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* subsequent writes.
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*/
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smp_mb__before_atomic();
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if (cmpxchg_relaxed(&pn->state, vcpu_halted, vcpu_hashed)
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!= vcpu_halted)
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return;
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/*
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* Put the lock into the hash table and set the _Q_SLOW_VAL.
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*
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* As this is the same vCPU that will check the _Q_SLOW_VAL value and
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* the hash table later on at unlock time, no atomic instruction is
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* needed.
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*/
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WRITE_ONCE(lock->locked, _Q_SLOW_VAL);
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(void)pv_hash(lock, pn);
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}
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/*
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* Wait for l->locked to become clear and acquire the lock;
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* halt the vcpu after a short spin.
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* __pv_queued_spin_unlock() will wake us.
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*
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* The current value of the lock will be returned for additional processing.
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*/
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static u32
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pv_wait_head_or_lock(struct qspinlock *lock, struct mcs_spinlock *node)
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{
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struct pv_node *pn = (struct pv_node *)node;
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struct qspinlock **lp = NULL;
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int waitcnt = 0;
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int loop;
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/*
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* If pv_kick_node() already advanced our state, we don't need to
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* insert ourselves into the hash table anymore.
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*/
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if (READ_ONCE(pn->state) == vcpu_hashed)
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lp = (struct qspinlock **)1;
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/*
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* Tracking # of slowpath locking operations
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*/
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lockevent_inc(lock_slowpath);
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for (;; waitcnt++) {
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/*
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* Set correct vCPU state to be used by queue node wait-early
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* mechanism.
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*/
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WRITE_ONCE(pn->state, vcpu_running);
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/*
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* Set the pending bit in the active lock spinning loop to
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* disable lock stealing before attempting to acquire the lock.
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*/
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set_pending(lock);
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for (loop = SPIN_THRESHOLD; loop; loop--) {
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if (trylock_clear_pending(lock))
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goto gotlock;
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cpu_relax();
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}
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clear_pending(lock);
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if (!lp) { /* ONCE */
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lp = pv_hash(lock, pn);
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/*
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* We must hash before setting _Q_SLOW_VAL, such that
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* when we observe _Q_SLOW_VAL in __pv_queued_spin_unlock()
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* we'll be sure to be able to observe our hash entry.
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*
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* [S] <hash> [Rmw] l->locked == _Q_SLOW_VAL
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* MB RMB
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* [RmW] l->locked = _Q_SLOW_VAL [L] <unhash>
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*
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* Matches the smp_rmb() in __pv_queued_spin_unlock().
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*/
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if (xchg(&lock->locked, _Q_SLOW_VAL) == 0) {
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/*
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* The lock was free and now we own the lock.
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* Change the lock value back to _Q_LOCKED_VAL
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* and unhash the table.
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*/
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WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);
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WRITE_ONCE(*lp, NULL);
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goto gotlock;
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}
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}
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WRITE_ONCE(pn->state, vcpu_hashed);
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lockevent_inc(pv_wait_head);
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lockevent_cond_inc(pv_wait_again, waitcnt);
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pv_wait(&lock->locked, _Q_SLOW_VAL);
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/*
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* Because of lock stealing, the queue head vCPU may not be
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* able to acquire the lock before it has to wait again.
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*/
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}
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/*
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* The cmpxchg() or xchg() call before coming here provides the
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* acquire semantics for locking. The dummy ORing of _Q_LOCKED_VAL
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* here is to indicate to the compiler that the value will always
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* be nozero to enable better code optimization.
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*/
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gotlock:
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return (u32)(atomic_read(&lock->val) | _Q_LOCKED_VAL);
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}
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/*
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* PV versions of the unlock fastpath and slowpath functions to be used
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* instead of queued_spin_unlock().
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*/
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__visible void
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__pv_queued_spin_unlock_slowpath(struct qspinlock *lock, u8 locked)
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{
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struct pv_node *node;
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if (unlikely(locked != _Q_SLOW_VAL)) {
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WARN(!debug_locks_silent,
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"pvqspinlock: lock 0x%lx has corrupted value 0x%x!\n",
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(unsigned long)lock, atomic_read(&lock->val));
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return;
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}
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/*
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* A failed cmpxchg doesn't provide any memory-ordering guarantees,
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* so we need a barrier to order the read of the node data in
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* pv_unhash *after* we've read the lock being _Q_SLOW_VAL.
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*
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* Matches the cmpxchg() in pv_wait_head_or_lock() setting _Q_SLOW_VAL.
|
*/
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smp_rmb();
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/*
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* Since the above failed to release, this must be the SLOW path.
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* Therefore start by looking up the blocked node and unhashing it.
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*/
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node = pv_unhash(lock);
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/*
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* Now that we have a reference to the (likely) blocked pv_node,
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* release the lock.
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*/
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smp_store_release(&lock->locked, 0);
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/*
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* At this point the memory pointed at by lock can be freed/reused,
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* however we can still use the pv_node to kick the CPU.
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* The other vCPU may not really be halted, but kicking an active
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* vCPU is harmless other than the additional latency in completing
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* the unlock.
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*/
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lockevent_inc(pv_kick_unlock);
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pv_kick(node->cpu);
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}
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/*
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* Include the architecture specific callee-save thunk of the
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* __pv_queued_spin_unlock(). This thunk is put together with
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* __pv_queued_spin_unlock() to make the callee-save thunk and the real unlock
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* function close to each other sharing consecutive instruction cachelines.
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* Alternatively, architecture specific version of __pv_queued_spin_unlock()
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* can be defined.
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*/
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#include <asm/qspinlock_paravirt.h>
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|
#ifndef __pv_queued_spin_unlock
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__visible void __pv_queued_spin_unlock(struct qspinlock *lock)
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{
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u8 locked;
|
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/*
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* We must not unlock if SLOW, because in that case we must first
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* unhash. Otherwise it would be possible to have multiple @lock
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* entries, which would be BAD.
|
*/
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locked = cmpxchg_release(&lock->locked, _Q_LOCKED_VAL, 0);
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if (likely(locked == _Q_LOCKED_VAL))
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return;
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__pv_queued_spin_unlock_slowpath(lock, locked);
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}
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#endif /* __pv_queued_spin_unlock */
|
