// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Queued spinlock
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*
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* (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
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* (C) Copyright 2013-2014,2018 Red Hat, Inc.
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* (C) Copyright 2015 Intel Corp.
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* (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
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*
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* Authors: Waiman Long <longman@redhat.com>
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* Peter Zijlstra <peterz@infradead.org>
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*/
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#ifndef _GEN_PV_LOCK_SLOWPATH
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#include <linux/smp.h>
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#include <linux/bug.h>
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#include <linux/cpumask.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <linux/mutex.h>
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#include <linux/prefetch.h>
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#include <asm/byteorder.h>
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#include <asm/qspinlock.h>
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/*
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* Include queued spinlock statistics code
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*/
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#include "qspinlock_stat.h"
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/*
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* The basic principle of a queue-based spinlock can best be understood
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* by studying a classic queue-based spinlock implementation called the
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* MCS lock. A copy of the original MCS lock paper ("Algorithms for Scalable
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* Synchronization on Shared-Memory Multiprocessors by Mellor-Crummey and
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* Scott") is available at
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*
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* https://bugzilla.kernel.org/show_bug.cgi?id=206115
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*
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* This queued spinlock implementation is based on the MCS lock, however to
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* make it fit the 4 bytes we assume spinlock_t to be, and preserve its
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* existing API, we must modify it somehow.
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*
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* In particular; where the traditional MCS lock consists of a tail pointer
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* (8 bytes) and needs the next pointer (another 8 bytes) of its own node to
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* unlock the next pending (next->locked), we compress both these: {tail,
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* next->locked} into a single u32 value.
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*
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* Since a spinlock disables recursion of its own context and there is a limit
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* to the contexts that can nest; namely: task, softirq, hardirq, nmi. As there
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* are at most 4 nesting levels, it can be encoded by a 2-bit number. Now
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* we can encode the tail by combining the 2-bit nesting level with the cpu
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* number. With one byte for the lock value and 3 bytes for the tail, only a
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* 32-bit word is now needed. Even though we only need 1 bit for the lock,
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* we extend it to a full byte to achieve better performance for architectures
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* that support atomic byte write.
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*
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* We also change the first spinner to spin on the lock bit instead of its
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* node; whereby avoiding the need to carry a node from lock to unlock, and
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* preserving existing lock API. This also makes the unlock code simpler and
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* faster.
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*
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* N.B. The current implementation only supports architectures that allow
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* atomic operations on smaller 8-bit and 16-bit data types.
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*
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*/
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#include "mcs_spinlock.h"
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#define MAX_NODES 4
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/*
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* On 64-bit architectures, the mcs_spinlock structure will be 16 bytes in
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* size and four of them will fit nicely in one 64-byte cacheline. For
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* pvqspinlock, however, we need more space for extra data. To accommodate
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* that, we insert two more long words to pad it up to 32 bytes. IOW, only
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* two of them can fit in a cacheline in this case. That is OK as it is rare
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* to have more than 2 levels of slowpath nesting in actual use. We don't
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* want to penalize pvqspinlocks to optimize for a rare case in native
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* qspinlocks.
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*/
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struct qnode {
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struct mcs_spinlock mcs;
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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long reserved[2];
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#endif
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};
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/*
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* The pending bit spinning loop count.
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* This heuristic is used to limit the number of lockword accesses
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* made by atomic_cond_read_relaxed when waiting for the lock to
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* transition out of the "== _Q_PENDING_VAL" state. We don't spin
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* indefinitely because there's no guarantee that we'll make forward
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* progress.
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*/
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#ifndef _Q_PENDING_LOOPS
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#define _Q_PENDING_LOOPS 1
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#endif
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/*
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* Per-CPU queue node structures; we can never have more than 4 nested
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* contexts: task, softirq, hardirq, nmi.
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*
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* Exactly fits one 64-byte cacheline on a 64-bit architecture.
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*
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* PV doubles the storage and uses the second cacheline for PV state.
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*/
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static DEFINE_PER_CPU_ALIGNED(struct qnode, qnodes[MAX_NODES]);
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/*
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* We must be able to distinguish between no-tail and the tail at 0:0,
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* therefore increment the cpu number by one.
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*/
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static inline __pure u32 encode_tail(int cpu, int idx)
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{
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u32 tail;
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tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
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tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
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return tail;
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}
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static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
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{
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int cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1;
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int idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
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return per_cpu_ptr(&qnodes[idx].mcs, cpu);
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}
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static inline __pure
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struct mcs_spinlock *grab_mcs_node(struct mcs_spinlock *base, int idx)
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{
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return &((struct qnode *)base + idx)->mcs;
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}
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#define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK)
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#if _Q_PENDING_BITS == 8
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/**
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* clear_pending - clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,* -> *,0,*
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*/
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static __always_inline void clear_pending(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->pending, 0);
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}
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*
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* Lock stealing is not allowed if this function is used.
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->locked_pending, _Q_LOCKED_VAL);
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}
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/*
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail), which heads an address dependency
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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/*
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* We can use relaxed semantics since the caller ensures that the
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* MCS node is properly initialized before updating the tail.
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*/
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return (u32)xchg_relaxed(&lock->tail,
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tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
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}
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#else /* _Q_PENDING_BITS == 8 */
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/**
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* clear_pending - clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,* -> *,0,*
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*/
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static __always_inline void clear_pending(struct qspinlock *lock)
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{
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atomic_andnot(_Q_PENDING_VAL, &lock->val);
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}
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val);
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}
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/**
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail)
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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u32 old, new, val = atomic_read(&lock->val);
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for (;;) {
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new = (val & _Q_LOCKED_PENDING_MASK) | tail;
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/*
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* We can use relaxed semantics since the caller ensures that
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* the MCS node is properly initialized before updating the
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* tail.
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*/
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old = atomic_cmpxchg_relaxed(&lock->val, val, new);
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if (old == val)
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break;
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val = old;
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}
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return old;
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}
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#endif /* _Q_PENDING_BITS == 8 */
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/**
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* queued_fetch_set_pending_acquire - fetch the whole lock value and set pending
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* @lock : Pointer to queued spinlock structure
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* Return: The previous lock value
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*
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* *,*,* -> *,1,*
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*/
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#ifndef queued_fetch_set_pending_acquire
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static __always_inline u32 queued_fetch_set_pending_acquire(struct qspinlock *lock)
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{
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return atomic_fetch_or_acquire(_Q_PENDING_VAL, &lock->val);
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}
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#endif
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/**
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* set_locked - Set the lock bit and own the lock
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* @lock: Pointer to queued spinlock structure
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*
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* *,*,0 -> *,0,1
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*/
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static __always_inline void set_locked(struct qspinlock *lock)
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{
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WRITE_ONCE(lock->locked, _Q_LOCKED_VAL);
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}
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/*
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* Generate the native code for queued_spin_unlock_slowpath(); provide NOPs for
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* all the PV callbacks.
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*/
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static __always_inline void __pv_init_node(struct mcs_spinlock *node) { }
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static __always_inline void __pv_wait_node(struct mcs_spinlock *node,
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struct mcs_spinlock *prev) { }
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static __always_inline void __pv_kick_node(struct qspinlock *lock,
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struct mcs_spinlock *node) { }
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static __always_inline u32 __pv_wait_head_or_lock(struct qspinlock *lock,
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struct mcs_spinlock *node)
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{ return 0; }
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#define pv_enabled() false
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#define pv_init_node __pv_init_node
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#define pv_wait_node __pv_wait_node
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#define pv_kick_node __pv_kick_node
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#define pv_wait_head_or_lock __pv_wait_head_or_lock
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define queued_spin_lock_slowpath native_queued_spin_lock_slowpath
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#endif
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#endif /* _GEN_PV_LOCK_SLOWPATH */
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/**
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* queued_spin_lock_slowpath - acquire the queued spinlock
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* @lock: Pointer to queued spinlock structure
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* @val: Current value of the queued spinlock 32-bit word
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*
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* (queue tail, pending bit, lock value)
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*
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* fast : slow : unlock
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* : :
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* uncontended (0,0,0) -:--> (0,0,1) ------------------------------:--> (*,*,0)
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* : | ^--------.------. / :
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* : v \ \ | :
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* pending : (0,1,1) +--> (0,1,0) \ | :
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* : | ^--' | | :
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* : v | | :
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* uncontended : (n,x,y) +--> (n,0,0) --' | :
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* queue : | ^--' | :
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* : v | :
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* contended : (*,x,y) +--> (*,0,0) ---> (*,0,1) -' :
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* queue : ^--' :
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*/
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void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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{
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struct mcs_spinlock *prev, *next, *node;
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u32 old, tail;
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int idx;
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BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS));
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if (pv_enabled())
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goto pv_queue;
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if (virt_spin_lock(lock))
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return;
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/*
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* Wait for in-progress pending->locked hand-overs with a bounded
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* number of spins so that we guarantee forward progress.
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*
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* 0,1,0 -> 0,0,1
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*/
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if (val == _Q_PENDING_VAL) {
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int cnt = _Q_PENDING_LOOPS;
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val = atomic_cond_read_relaxed(&lock->val,
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(VAL != _Q_PENDING_VAL) || !cnt--);
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}
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/*
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* If we observe any contention; queue.
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*/
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if (val & ~_Q_LOCKED_MASK)
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goto queue;
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/*
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* trylock || pending
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*
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* 0,0,* -> 0,1,* -> 0,0,1 pending, trylock
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*/
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val = queued_fetch_set_pending_acquire(lock);
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/*
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* If we observe contention, there is a concurrent locker.
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*
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* Undo and queue; our setting of PENDING might have made the
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* n,0,0 -> 0,0,0 transition fail and it will now be waiting
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* on @next to become !NULL.
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*/
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if (unlikely(val & ~_Q_LOCKED_MASK)) {
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/* Undo PENDING if we set it. */
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if (!(val & _Q_PENDING_MASK))
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clear_pending(lock);
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goto queue;
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}
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/*
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* We're pending, wait for the owner to go away.
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*
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* 0,1,1 -> 0,1,0
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*
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* this wait loop must be a load-acquire such that we match the
|
* store-release that clears the locked bit and create lock
|
* sequentiality; this is because not all
|
* clear_pending_set_locked() implementations imply full
|
* barriers.
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*/
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if (val & _Q_LOCKED_MASK)
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atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_MASK));
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/*
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* take ownership and clear the pending bit.
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*
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* 0,1,0 -> 0,0,1
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*/
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clear_pending_set_locked(lock);
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lockevent_inc(lock_pending);
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return;
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|
/*
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* End of pending bit optimistic spinning and beginning of MCS
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* queuing.
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*/
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queue:
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lockevent_inc(lock_slowpath);
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pv_queue:
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node = this_cpu_ptr(&qnodes[0].mcs);
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idx = node->count++;
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tail = encode_tail(smp_processor_id(), idx);
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/*
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* 4 nodes are allocated based on the assumption that there will
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* not be nested NMIs taking spinlocks. That may not be true in
|
* some architectures even though the chance of needing more than
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* 4 nodes will still be extremely unlikely. When that happens,
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* we fall back to spinning on the lock directly without using
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* any MCS node. This is not the most elegant solution, but is
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* simple enough.
|
*/
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if (unlikely(idx >= MAX_NODES)) {
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lockevent_inc(lock_no_node);
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while (!queued_spin_trylock(lock))
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cpu_relax();
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goto release;
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}
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node = grab_mcs_node(node, idx);
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/*
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* Keep counts of non-zero index values:
|
*/
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lockevent_cond_inc(lock_use_node2 + idx - 1, idx);
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/*
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* Ensure that we increment the head node->count before initialising
|
* the actual node. If the compiler is kind enough to reorder these
|
* stores, then an IRQ could overwrite our assignments.
|
*/
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barrier();
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node->locked = 0;
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node->next = NULL;
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pv_init_node(node);
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|
/*
|
* We touched a (possibly) cold cacheline in the per-cpu queue node;
|
* attempt the trylock once more in the hope someone let go while we
|
* weren't watching.
|
*/
|
if (queued_spin_trylock(lock))
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goto release;
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|
/*
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* Ensure that the initialisation of @node is complete before we
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* publish the updated tail via xchg_tail() and potentially link
|
* @node into the waitqueue via WRITE_ONCE(prev->next, node) below.
|
*/
|
smp_wmb();
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|
/*
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* Publish the updated tail.
|
* We have already touched the queueing cacheline; don't bother with
|
* pending stuff.
|
*
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* p,*,* -> n,*,*
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*/
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old = xchg_tail(lock, tail);
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next = NULL;
|
|
/*
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* if there was a previous node; link it and wait until reaching the
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* head of the waitqueue.
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*/
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if (old & _Q_TAIL_MASK) {
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prev = decode_tail(old);
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/* Link @node into the waitqueue. */
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WRITE_ONCE(prev->next, node);
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pv_wait_node(node, prev);
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arch_mcs_spin_lock_contended(&node->locked);
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|
/*
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* While waiting for the MCS lock, the next pointer may have
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* been set by another lock waiter. We optimistically load
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* the next pointer & prefetch the cacheline for writing
|
* to reduce latency in the upcoming MCS unlock operation.
|
*/
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next = READ_ONCE(node->next);
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if (next)
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prefetchw(next);
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}
|
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/*
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* we're at the head of the waitqueue, wait for the owner & pending to
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* go away.
|
*
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* *,x,y -> *,0,0
|
*
|
* this wait loop must use a load-acquire such that we match the
|
* store-release that clears the locked bit and create lock
|
* sequentiality; this is because the set_locked() function below
|
* does not imply a full barrier.
|
*
|
* The PV pv_wait_head_or_lock function, if active, will acquire
|
* the lock and return a non-zero value. So we have to skip the
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* atomic_cond_read_acquire() call. As the next PV queue head hasn't
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* been designated yet, there is no way for the locked value to become
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* _Q_SLOW_VAL. So both the set_locked() and the
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* atomic_cmpxchg_relaxed() calls will be safe.
|
*
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* If PV isn't active, 0 will be returned instead.
|
*
|
*/
|
if ((val = pv_wait_head_or_lock(lock, node)))
|
goto locked;
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|
val = atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK));
|
|
locked:
|
/*
|
* claim the lock:
|
*
|
* n,0,0 -> 0,0,1 : lock, uncontended
|
* *,*,0 -> *,*,1 : lock, contended
|
*
|
* If the queue head is the only one in the queue (lock value == tail)
|
* and nobody is pending, clear the tail code and grab the lock.
|
* Otherwise, we only need to grab the lock.
|
*/
|
|
/*
|
* In the PV case we might already have _Q_LOCKED_VAL set, because
|
* of lock stealing; therefore we must also allow:
|
*
|
* n,0,1 -> 0,0,1
|
*
|
* Note: at this point: (val & _Q_PENDING_MASK) == 0, because of the
|
* above wait condition, therefore any concurrent setting of
|
* PENDING will make the uncontended transition fail.
|
*/
|
if ((val & _Q_TAIL_MASK) == tail) {
|
if (atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL))
|
goto release; /* No contention */
|
}
|
|
/*
|
* Either somebody is queued behind us or _Q_PENDING_VAL got set
|
* which will then detect the remaining tail and queue behind us
|
* ensuring we'll see a @next.
|
*/
|
set_locked(lock);
|
|
/*
|
* contended path; wait for next if not observed yet, release.
|
*/
|
if (!next)
|
next = smp_cond_load_relaxed(&node->next, (VAL));
|
|
arch_mcs_spin_unlock_contended(&next->locked);
|
pv_kick_node(lock, next);
|
|
release:
|
/*
|
* release the node
|
*/
|
__this_cpu_dec(qnodes[0].mcs.count);
|
}
|
EXPORT_SYMBOL(queued_spin_lock_slowpath);
|
|
/*
|
* Generate the paravirt code for queued_spin_unlock_slowpath().
|
*/
|
#if !defined(_GEN_PV_LOCK_SLOWPATH) && defined(CONFIG_PARAVIRT_SPINLOCKS)
|
#define _GEN_PV_LOCK_SLOWPATH
|
|
#undef pv_enabled
|
#define pv_enabled() true
|
|
#undef pv_init_node
|
#undef pv_wait_node
|
#undef pv_kick_node
|
#undef pv_wait_head_or_lock
|
|
#undef queued_spin_lock_slowpath
|
#define queued_spin_lock_slowpath __pv_queued_spin_lock_slowpath
|
|
#include "qspinlock_paravirt.h"
|
#include "qspinlock.c"
|
|
bool nopvspin __initdata;
|
static __init int parse_nopvspin(char *arg)
|
{
|
nopvspin = true;
|
return 0;
|
}
|
early_param("nopvspin", parse_nopvspin);
|
#endif
|
