// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014 Intel Corp.
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* Author: Jiang Liu <jiang.liu@linux.intel.com>
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*
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* This file is licensed under GPLv2.
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*
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* This file contains common code to support Message Signalled Interrupt for
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* PCI compatible and non PCI compatible devices.
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*/
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/slab.h>
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#include "internals.h"
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/**
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* alloc_msi_entry - Allocate an initialize msi_entry
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* @dev: Pointer to the device for which this is allocated
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* @nvec: The number of vectors used in this entry
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* @affinity: Optional pointer to an affinity mask array size of @nvec
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*
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* If @affinity is not NULL then an affinity array[@nvec] is allocated
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* and the affinity masks and flags from @affinity are copied.
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*/
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struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
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const struct irq_affinity_desc *affinity)
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{
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struct msi_desc *desc;
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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return NULL;
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INIT_LIST_HEAD(&desc->list);
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desc->dev = dev;
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desc->nvec_used = nvec;
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if (affinity) {
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desc->affinity = kmemdup(affinity,
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nvec * sizeof(*desc->affinity), GFP_KERNEL);
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if (!desc->affinity) {
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kfree(desc);
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return NULL;
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}
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}
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return desc;
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}
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void free_msi_entry(struct msi_desc *entry)
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{
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kfree(entry->affinity);
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kfree(entry);
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}
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void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
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{
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*msg = entry->msg;
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}
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void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
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{
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struct msi_desc *entry = irq_get_msi_desc(irq);
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__get_cached_msi_msg(entry, msg);
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}
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EXPORT_SYMBOL_GPL(get_cached_msi_msg);
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#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
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static inline void irq_chip_write_msi_msg(struct irq_data *data,
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struct msi_msg *msg)
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{
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data->chip->irq_write_msi_msg(data, msg);
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}
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static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
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{
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struct msi_domain_info *info = domain->host_data;
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/*
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* If the MSI provider has messed with the second message and
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* not advertized that it is level-capable, signal the breakage.
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*/
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WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
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(info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
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(msg[1].address_lo || msg[1].address_hi || msg[1].data));
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}
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/**
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* msi_domain_set_affinity - Generic affinity setter function for MSI domains
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* @irq_data: The irq data associated to the interrupt
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* @mask: The affinity mask to set
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* @force: Flag to enforce setting (disable online checks)
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*
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* Intended to be used by MSI interrupt controllers which are
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* implemented with hierarchical domains.
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*/
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int msi_domain_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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struct irq_data *parent = irq_data->parent_data;
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struct msi_msg msg[2] = { [1] = { }, };
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int ret;
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ret = parent->chip->irq_set_affinity(parent, mask, force);
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if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
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BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
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msi_check_level(irq_data->domain, msg);
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irq_chip_write_msi_msg(irq_data, msg);
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}
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return ret;
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}
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static int msi_domain_activate(struct irq_domain *domain,
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struct irq_data *irq_data, bool early)
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{
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struct msi_msg msg[2] = { [1] = { }, };
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BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
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msi_check_level(irq_data->domain, msg);
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irq_chip_write_msi_msg(irq_data, msg);
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return 0;
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}
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static void msi_domain_deactivate(struct irq_domain *domain,
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struct irq_data *irq_data)
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{
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struct msi_msg msg[2];
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memset(msg, 0, sizeof(msg));
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irq_chip_write_msi_msg(irq_data, msg);
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}
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static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct msi_domain_info *info = domain->host_data;
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struct msi_domain_ops *ops = info->ops;
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irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
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int i, ret;
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if (irq_find_mapping(domain, hwirq) > 0)
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return -EEXIST;
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if (domain->parent) {
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
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if (ret < 0)
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return ret;
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}
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for (i = 0; i < nr_irqs; i++) {
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ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
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if (ret < 0) {
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if (ops->msi_free) {
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for (i--; i > 0; i--)
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ops->msi_free(domain, info, virq + i);
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}
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irq_domain_free_irqs_top(domain, virq, nr_irqs);
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return ret;
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}
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}
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return 0;
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}
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static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct msi_domain_info *info = domain->host_data;
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int i;
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if (info->ops->msi_free) {
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for (i = 0; i < nr_irqs; i++)
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info->ops->msi_free(domain, info, virq + i);
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}
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irq_domain_free_irqs_top(domain, virq, nr_irqs);
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.alloc = msi_domain_alloc,
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.free = msi_domain_free,
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.activate = msi_domain_activate,
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.deactivate = msi_domain_deactivate,
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};
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static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
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msi_alloc_info_t *arg)
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{
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return arg->hwirq;
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}
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static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *arg)
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{
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memset(arg, 0, sizeof(*arg));
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return 0;
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}
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static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
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struct msi_desc *desc)
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{
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arg->desc = desc;
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}
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static int msi_domain_ops_init(struct irq_domain *domain,
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struct msi_domain_info *info,
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unsigned int virq, irq_hw_number_t hwirq,
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msi_alloc_info_t *arg)
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{
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
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info->chip_data);
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if (info->handler && info->handler_name) {
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__irq_set_handler(virq, info->handler, 0, info->handler_name);
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if (info->handler_data)
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irq_set_handler_data(virq, info->handler_data);
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}
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return 0;
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}
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static int msi_domain_ops_check(struct irq_domain *domain,
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struct msi_domain_info *info,
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struct device *dev)
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{
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return 0;
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}
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static struct msi_domain_ops msi_domain_ops_default = {
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.get_hwirq = msi_domain_ops_get_hwirq,
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.msi_init = msi_domain_ops_init,
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.msi_check = msi_domain_ops_check,
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.msi_prepare = msi_domain_ops_prepare,
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.set_desc = msi_domain_ops_set_desc,
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.domain_alloc_irqs = __msi_domain_alloc_irqs,
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.domain_free_irqs = __msi_domain_free_irqs,
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};
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static void msi_domain_update_dom_ops(struct msi_domain_info *info)
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{
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struct msi_domain_ops *ops = info->ops;
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if (ops == NULL) {
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info->ops = &msi_domain_ops_default;
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return;
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}
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if (ops->domain_alloc_irqs == NULL)
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ops->domain_alloc_irqs = msi_domain_ops_default.domain_alloc_irqs;
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if (ops->domain_free_irqs == NULL)
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ops->domain_free_irqs = msi_domain_ops_default.domain_free_irqs;
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if (!(info->flags & MSI_FLAG_USE_DEF_DOM_OPS))
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return;
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if (ops->get_hwirq == NULL)
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ops->get_hwirq = msi_domain_ops_default.get_hwirq;
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if (ops->msi_init == NULL)
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ops->msi_init = msi_domain_ops_default.msi_init;
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if (ops->msi_check == NULL)
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ops->msi_check = msi_domain_ops_default.msi_check;
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if (ops->msi_prepare == NULL)
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ops->msi_prepare = msi_domain_ops_default.msi_prepare;
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if (ops->set_desc == NULL)
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ops->set_desc = msi_domain_ops_default.set_desc;
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}
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static void msi_domain_update_chip_ops(struct msi_domain_info *info)
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{
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struct irq_chip *chip = info->chip;
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BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
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if (!chip->irq_set_affinity)
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chip->irq_set_affinity = msi_domain_set_affinity;
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}
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/**
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* msi_create_irq_domain - Create a MSI interrupt domain
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* @fwnode: Optional fwnode of the interrupt controller
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* @info: MSI domain info
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* @parent: Parent irq domain
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*/
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struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
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struct msi_domain_info *info,
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struct irq_domain *parent)
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{
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struct irq_domain *domain;
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msi_domain_update_dom_ops(info);
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if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
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msi_domain_update_chip_ops(info);
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domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
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fwnode, &msi_domain_ops, info);
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if (domain && !domain->name && info->chip)
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domain->name = info->chip->name;
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return domain;
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}
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int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *arg)
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{
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struct msi_domain_info *info = domain->host_data;
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struct msi_domain_ops *ops = info->ops;
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int ret;
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ret = ops->msi_check(domain, info, dev);
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if (ret == 0)
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ret = ops->msi_prepare(domain, dev, nvec, arg);
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return ret;
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}
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int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
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int virq, int nvec, msi_alloc_info_t *arg)
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{
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struct msi_domain_info *info = domain->host_data;
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struct msi_domain_ops *ops = info->ops;
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struct msi_desc *desc;
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int ret = 0;
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for_each_msi_entry(desc, dev) {
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/* Don't even try the multi-MSI brain damage. */
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if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
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ret = -EINVAL;
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break;
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}
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if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
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continue;
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ops->set_desc(arg, desc);
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/* Assumes the domain mutex is held! */
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ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
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arg);
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if (ret)
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break;
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irq_set_msi_desc_off(desc->irq, 0, desc);
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}
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if (ret) {
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/* Mop up the damage */
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for_each_msi_entry(desc, dev) {
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if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
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continue;
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irq_domain_free_irqs_common(domain, desc->irq, 1);
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}
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}
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return ret;
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}
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/*
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* Carefully check whether the device can use reservation mode. If
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* reservation mode is enabled then the early activation will assign a
|
* dummy vector to the device. If the PCI/MSI device does not support
|
* masking of the entry then this can result in spurious interrupts when
|
* the device driver is not absolutely careful. But even then a malfunction
|
* of the hardware could result in a spurious interrupt on the dummy vector
|
* and render the device unusable. If the entry can be masked then the core
|
* logic will prevent the spurious interrupt and reservation mode can be
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* used. For now reservation mode is restricted to PCI/MSI.
|
*/
|
static bool msi_check_reservation_mode(struct irq_domain *domain,
|
struct msi_domain_info *info,
|
struct device *dev)
|
{
|
struct msi_desc *desc;
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|
switch(domain->bus_token) {
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case DOMAIN_BUS_PCI_MSI:
|
case DOMAIN_BUS_VMD_MSI:
|
break;
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default:
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return false;
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}
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if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
|
return false;
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if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
|
return false;
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/*
|
* Checking the first MSI descriptor is sufficient. MSIX supports
|
* masking and MSI does so when the maskbit is set.
|
*/
|
desc = first_msi_entry(dev);
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return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit;
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}
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int __msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
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int nvec)
|
{
|
struct msi_domain_info *info = domain->host_data;
|
struct msi_domain_ops *ops = info->ops;
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struct irq_data *irq_data;
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struct msi_desc *desc;
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msi_alloc_info_t arg;
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int i, ret, virq;
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bool can_reserve;
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ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
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if (ret)
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return ret;
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for_each_msi_entry(desc, dev) {
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ops->set_desc(&arg, desc);
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virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
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dev_to_node(dev), &arg, false,
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desc->affinity);
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if (virq < 0) {
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ret = -ENOSPC;
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if (ops->handle_error)
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ret = ops->handle_error(domain, desc, ret);
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if (ops->msi_finish)
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ops->msi_finish(&arg, ret);
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return ret;
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}
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for (i = 0; i < desc->nvec_used; i++) {
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irq_set_msi_desc_off(virq, i, desc);
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irq_debugfs_copy_devname(virq + i, dev);
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}
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}
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|
if (ops->msi_finish)
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ops->msi_finish(&arg, 0);
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can_reserve = msi_check_reservation_mode(domain, info, dev);
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|
/*
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* This flag is set by the PCI layer as we need to activate
|
* the MSI entries before the PCI layer enables MSI in the
|
* card. Otherwise the card latches a random msi message.
|
*/
|
if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
|
goto skip_activate;
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for_each_msi_vector(desc, i, dev) {
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if (desc->irq == i) {
|
virq = desc->irq;
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dev_dbg(dev, "irq [%d-%d] for MSI\n",
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virq, virq + desc->nvec_used - 1);
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}
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irq_data = irq_domain_get_irq_data(domain, i);
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if (!can_reserve) {
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irqd_clr_can_reserve(irq_data);
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if (domain->flags & IRQ_DOMAIN_MSI_NOMASK_QUIRK)
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irqd_set_msi_nomask_quirk(irq_data);
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if ((info->flags & MSI_FLAG_ACTIVATE_EARLY) &&
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irqd_affinity_is_managed(irq_data) &&
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!cpumask_intersects(irq_data_get_affinity_mask(irq_data),
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cpu_online_mask)) {
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irqd_set_managed_shutdown(irq_data);
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continue;
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}
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}
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ret = irq_domain_activate_irq(irq_data, can_reserve);
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if (ret)
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goto cleanup;
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}
|
|
skip_activate:
|
/*
|
* If these interrupts use reservation mode, clear the activated bit
|
* so request_irq() will assign the final vector.
|
*/
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if (can_reserve) {
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for_each_msi_vector(desc, i, dev) {
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irq_data = irq_domain_get_irq_data(domain, i);
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irqd_clr_activated(irq_data);
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}
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}
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return 0;
|
|
cleanup:
|
msi_domain_free_irqs(domain, dev);
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return ret;
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}
|
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/**
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* msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
|
* @domain: The domain to allocate from
|
* @dev: Pointer to device struct of the device for which the interrupts
|
* are allocated
|
* @nvec: The number of interrupts to allocate
|
*
|
* Returns 0 on success or an error code.
|
*/
|
int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
|
int nvec)
|
{
|
struct msi_domain_info *info = domain->host_data;
|
struct msi_domain_ops *ops = info->ops;
|
|
return ops->domain_alloc_irqs(domain, dev, nvec);
|
}
|
|
void __msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
|
{
|
struct irq_data *irq_data;
|
struct msi_desc *desc;
|
int i;
|
|
for_each_msi_vector(desc, i, dev) {
|
irq_data = irq_domain_get_irq_data(domain, i);
|
if (irqd_is_activated(irq_data))
|
irq_domain_deactivate_irq(irq_data);
|
}
|
|
for_each_msi_entry(desc, dev) {
|
/*
|
* We might have failed to allocate an MSI early
|
* enough that there is no IRQ associated to this
|
* entry. If that's the case, don't do anything.
|
*/
|
if (desc->irq) {
|
irq_domain_free_irqs(desc->irq, desc->nvec_used);
|
desc->irq = 0;
|
}
|
}
|
}
|
|
/**
|
* __msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
|
* @domain: The domain to managing the interrupts
|
* @dev: Pointer to device struct of the device for which the interrupts
|
* are free
|
*/
|
void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
|
{
|
struct msi_domain_info *info = domain->host_data;
|
struct msi_domain_ops *ops = info->ops;
|
|
return ops->domain_free_irqs(domain, dev);
|
}
|
|
/**
|
* msi_get_domain_info - Get the MSI interrupt domain info for @domain
|
* @domain: The interrupt domain to retrieve data from
|
*
|
* Returns the pointer to the msi_domain_info stored in
|
* @domain->host_data.
|
*/
|
struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
|
{
|
return (struct msi_domain_info *)domain->host_data;
|
}
|
|
#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */
|
